Lines Matching +full:interrupt +full:- +full:affinity
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <[email protected]>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
30 interrupt-controller: true
32 "#address-cells":
34 "#size-cells":
39 "#interrupt-cells":
41 Specifies the number of cells needed to encode an interrupt source.
43 If the system requires describing PPI affinity, then the value must
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
50 The 2nd cell contains the interrupt number for the interrupt type.
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
61 interrupt is affine to. The interrupt must be a PPI, and the node
62 pointed must be a subnode of the "ppi-partitions" subnode. For
63 interrupt types other than PPI or PPIs that are not partitioned,
64 this cell must be zero. See the "ppi-partitions" node description
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
91 Interrupt source of the VGIC maintenance interrupt.
94 redistributor-stride:
102 "#redistributor-regions":
109 dma-noncoherent:
112 and cacheability attributes but are connected to a non-coherent
115 msi-controller:
117 Only present if the Message Based Interrupt functionality is
118 being exposed by the HW, and the mbi-ranges property present.
120 mbi-ranges:
125 $ref: /schemas/types.yaml#/definitions/uint32-matrix
130 mbi-alias:
136 - $ref: /schemas/types.yaml#/definitions/uint32
137 - $ref: /schemas/types.yaml#/definitions/uint64
139 ppi-partitions:
143 PPI affinity can be expressed as a single "ppi-partitions" node,
144 containing a set of sub-nodes.
146 "^interrupt-partition-[0-9]+$":
150 affinity:
151 $ref: /schemas/types.yaml#/definitions/phandle-array
159 - affinity
164 clock-names:
166 - const: aclk
168 power-domains:
174 mediatek,broken-save-restore-fw:
181 mbi-ranges: [ msi-controller ]
182 msi-controller: [ mbi-ranges ]
185 - compatible
186 - reg
189 "^gic-its@": false
190 "^interrupt-controller@[0-9a-f]+$": false
191 # msi-controller is preferred, but allow other names
192 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
195 GICv3 has one or more Interrupt Translation Services (ITS) that are
199 const: arm,gic-v3-its
201 dma-noncoherent:
204 cacheability attributes but is connected to a non-coherent
207 msi-controller: true
209 "#msi-cells":
211 The single msi-cell is the DeviceID of the device which will generate
220 socionext,synquacer-pre-its:
223 address and size of the pre-ITS window.
224 $ref: /schemas/types.yaml#/definitions/uint32-array
229 - compatible
230 - msi-controller
231 - "#msi-cells"
232 - reg
239 - |
240 gic: interrupt-controller@2cf00000 {
241 compatible = "arm,gic-v3";
242 #interrupt-cells = <3>;
243 #address-cells = <1>;
244 #size-cells = <1>;
246 interrupt-controller;
254 msi-controller;
255 mbi-ranges = <256 128>;
257 msi-controller@2c200000 {
258 compatible = "arm,gic-v3-its";
259 msi-controller;
260 #msi-cells = <1>;
265 - |
266 interrupt-controller@2c010000 {
267 compatible = "arm,gic-v3";
268 #interrupt-cells = <4>;
269 #address-cells = <1>;
270 #size-cells = <1>;
272 interrupt-controller;
273 redistributor-stride = <0x0 0x40000>; // 256kB stride
274 #redistributor-regions = <2>;
276 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
277 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
283 msi-controller@2c200000 {
284 compatible = "arm,gic-v3-its";
285 msi-controller;
286 #msi-cells = <1>;
290 msi-controller@2c400000 {
291 compatible = "arm,gic-v3-its";
292 msi-controller;
293 #msi-cells = <1>;
297 ppi-partitions {
298 part0: interrupt-partition-0 {
299 affinity = <&cpu0>, <&cpu2>;
302 part1: interrupt-partition-1 {
303 affinity = <&cpu1>, <&cpu3>;