Lines Matching +full:resolver +full:- +full:to +full:- +full:digital

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S90 Resolver-to-Digital Converter
10   - Matheus Tavares <[email protected]>
22   spi-max-frequency:
26       delay is expected between the application of a logic LO to CS and the
28       implemented in the spi code, to satisfy it, SCLK's period should be at
29       most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
32   spi-cpol: true
34   spi-cpha: true
37   - compatible
38   - reg
41   spi-cpol: [ spi-cpha ]
42   spi-cpha: [ spi-cpol ]
45   - $ref: /schemas/spi/spi-peripheral-props.yaml#
50   - |
52         #address-cells = <1>;
53         #size-cells = <0>;
55         resolver@0 {
58             spi-max-frequency = <830000>;
59             spi-cpol;
60             spi-cpha;