Lines Matching +full:nand +full:- +full:style
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <[email protected]>
11 - Bartosz Golaszewski <[email protected]>
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17 NAND-style parallel busses.
22 - brcm,bcm6345-gpio
23 - ni,169445-nand-gpio
24 - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
26 big-endian: true
28 '#gpio-cells':
31 gpio-controller: true
33 little-endian: true
43 - description:
48 - description:
51 - description:
56 - description:
60 - description:
65 reg-names:
70 - dat
71 - set
72 - clr
73 - dirout
74 - dirin
76 native-endian: true
87 no-output:
93 - compatible
94 - reg
95 - reg-names
96 - '#gpio-cells'
97 - gpio-controller
102 - |
104 compatible = "ni,169445-nand-gpio";
106 reg-names = "dat";
107 gpio-controller;
108 #gpio-cells = <2>;
112 compatible = "wd,mbl-gpio";
113 reg-names = "dat";
115 #gpio-cells = <2>;
116 gpio-controller;
117 no-output;
121 compatible = "brcm,bcm6345-gpio";
122 reg-names = "dirout", "dat";
125 native-endian;
126 gpio-controller;
127 #gpio-cells = <2>;