Lines Matching +full:gpio +full:- +full:line
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic MMIO GPIO
10 - Linus Walleij <[email protected]>
11 - Bartosz Golaszewski <[email protected]>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17 NAND-style parallel busses.
22 - brcm,bcm6345-gpio
23 - ni,169445-nand-gpio
24 - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
26 big-endian: true
28 '#gpio-cells':
31 gpio-controller: true
33 little-endian: true
40 of GPIOs is set by the width, with bit 0 corresponding to GPIO 0, unless
43 - description:
44 Register to READ the value of the GPIO lines. If GPIO line is high,
45 the bit will be set. If the GPIO line is low, the bit will be cleared.
48 - description:
49 Register to SET the value of the GPIO lines. Setting a bit in this
50 register will drive the GPIO line high.
51 - description:
52 Register to CLEAR the value of the GPIO lines. Setting a bit in this
53 register will drive the GPIO line low. If this register is omitted,
54 the SET register will be used to clear the GPIO lines as well, by
55 actively writing the line with 0.
56 - description:
57 Register to set the line as OUTPUT. Setting a bit in this register
58 will turn that line into an output line. Conversely, clearing a bit
59 will turn that line into an input.
60 - description:
61 Register to set this line as INPUT. Setting a bit in this register
62 will turn that line into an input line. Conversely, clearing a bit
63 will turn that line into an output.
65 reg-names:
70 - dat
71 - set
72 - clr
73 - dirout
74 - dirin
76 native-endian: true
82 If this property is present the number of usable GPIO lines are restricted
83 to the first 0 .. ngpios lines. This is useful when the GPIO MMIO register
84 has 32 bits for GPIO but only the first 12 are actually connected to
87 no-output:
90 If this property is present, the controller cannot drive the GPIO lines.
93 - compatible
94 - reg
95 - reg-names
96 - '#gpio-cells'
97 - gpio-controller
102 - |
103 gpio@1f300010 {
104 compatible = "ni,169445-nand-gpio";
106 reg-names = "dat";
107 gpio-controller;
108 #gpio-cells = <2>;
111 gpio@e0100000 {
112 compatible = "wd,mbl-gpio";
113 reg-names = "dat";
115 #gpio-cells = <2>;
116 gpio-controller;
117 no-output;
120 gpio@fffe0406 {
121 compatible = "brcm,bcm6345-gpio";
122 reg-names = "dirout", "dat";
125 native-endian;
126 gpio-controller;
127 #gpio-cells = <2>;