Lines Matching +full:gpio +full:- +full:bank +full:- +full:widths
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
11 registers with each set controlling a bank of up to 32 pins. A single
15 - Doug Berger <[email protected]>
16 - Florian Fainelli <[email protected]>
21 - enum:
22 - brcm,bcm7445-gpio
23 - const: brcm,brcmstb-gpio
29 the brcmstb GPIO controller registers
31 "#gpio-cells":
36 bit[0]: polarity (0 for active-high, 1 for active-low)
38 gpio-controller: true
40 brcm,gpio-bank-widths:
41 $ref: /schemas/types.yaml#/definitions/uint32-array
43 Number of GPIO lines for each bank. Number of elements must
49 The interrupt shared by all GPIO lines for this controller.
51 "#interrupt-cells":
54 The first cell is the GPIO number, the second should specify
56 - bits[3:0] trigger type and level flags
57 1 = low-to-high edge triggered
58 2 = high-to-low edge triggered
59 4 = active high level-sensitive
60 8 = active low level-sensitive
63 interrupt-controller: true
65 gpio-ranges: true
67 gpio-line-names:
71 wakeup-source:
77 - compatible
78 - reg
79 - gpio-controller
80 - "#gpio-cells"
81 - brcm,gpio-bank-widths
86 - |
87 upg_gio: gpio@f040a700 {
88 #gpio-cells = <2>;
89 #interrupt-cells = <2>;
90 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
91 gpio-controller;
92 interrupt-controller;
94 interrupt-parent = <&irq0_intc>;
96 brcm,gpio-bank-widths = <32 32 32 24>;
97 gpio-ranges = <&pinctrl 0 0 120>;
100 upg_gio_aon: gpio@f04172c0 {
101 #gpio-cells = <2>;
102 #interrupt-cells = <2>;
103 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
104 gpio-controller;
105 interrupt-controller;
107 interrupt-parent = <&irq0_aon_intc>;
109 wakeup-source;
110 brcm,gpio-bank-widths = <18 4>;