Lines Matching +full:optee +full:- +full:channel +full:- +full:id
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <[email protected]>
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
34 - description: SCMI compliant firmware with mailbox transport
36 - const: arm,scmi
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
39 - const: arm,scmi-smc
40 - description: SCMI compliant firmware with ARM SMC/HVC transport
41 with shmem address(4KB-page, offset) as parameters
43 - const: arm,scmi-smc-param
44 - description: SCMI compliant firmware with Qualcomm SMC/HVC transport
46 - const: qcom,scmi-smc
47 - description: SCMI compliant firmware with SCMI Virtio transport.
50 - const: arm,scmi-virtio
51 - description: SCMI compliant firmware with OP-TEE transport
53 - const: linaro,scmi-optee
62 interrupt-names:
65 mbox-names:
70 - items:
71 - const: tx
72 - const: rx
74 - items:
75 - const: tx
76 - const: tx_reply
77 - const: rx
78 - const: rx_reply
83 List of phandle and mailbox channel specifiers. It should contain
91 one single channel descriptor is enough if such channel is bidirectional,
92 while two channel descriptors are needed to represent the SCMI ("tx")
93 channel if the underlying mailbox channels are of unidirectional type.
97 1 mbox / 1 shmem => SCMI TX over 1 mailbox bidirectional channel
109 transport channel specified.
113 '#address-cells':
116 '#size-cells':
119 atomic-threshold-us:
123 an higher-than-threshold execution latency, should not be considered for
127 arm,max-rx-timeout-ms:
130 transport maximum timeout value for the receive channel. The value should
131 be a non-zero value if set.
134 arm,max-msg-size:
140 arm,max-msg:
143 An optional value representing the maximum number of concurrent in-flight
146 this platform. If set, the value should be non-zero.
149 arm,smc-id:
152 SMC id required when using smc or hvc transports
154 linaro,optee-channel-id:
157 Channel specifier required when using OP-TEE transport.
160 $ref: '#/$defs/protocol-node'
167 '#power-domain-cells':
171 - '#power-domain-cells'
174 $ref: '#/$defs/protocol-node'
182 $ref: '#/$defs/protocol-node'
189 '#clock-cells':
192 '#power-domain-cells':
196 - required:
197 - '#clock-cells'
199 - required:
200 - '#power-domain-cells'
203 $ref: '#/$defs/protocol-node'
210 '#clock-cells':
214 - '#clock-cells'
217 $ref: '#/$defs/protocol-node'
224 '#thermal-sensor-cells':
228 - '#thermal-sensor-cells'
231 $ref: '#/$defs/protocol-node'
238 '#reset-cells':
242 - '#reset-cells'
245 $ref: '#/$defs/protocol-node'
259 '#address-cells':
262 '#size-cells':
266 '^regulator@[0-9a-f]+$':
277 - reg
280 $ref: '#/$defs/protocol-node'
290 - $ref: '#/$defs/protocol-node'
291 - anyOf:
292 - $ref: /schemas/pinctrl/pinctrl.yaml
293 - $ref: /schemas/firmware/nxp,imx95-scmi-pinctrl.yaml
302 '-pins$':
305 - $ref: /schemas/pinctrl/pincfg-node.yaml#
306 - $ref: /schemas/pinctrl/pinmux-node.yaml#
310 A pin multiplexing sub-node describes how to configure a
312 A single sub-node may define several pin configurations.
313 This sub-node is using the default pinctrl bindings to configure
318 - reg
323 protocol-node:
326 Each sub-node represents a protocol supported. If the platform
327 supports a dedicated communication channel for a particular protocol,
329 The virtio transport does not support a dedicated communication channel.
335 mbox-names:
337 - items:
338 - const: tx
339 - const: rx
341 - items:
342 - const: tx
343 - const: tx_reply
344 - const: rx
355 linaro,optee-channel-id:
358 Channel specifier required when using OP-TEE transport and
359 protocol has a dedicated communication channel.
362 - reg
365 - compatible
375 interrupt-names: false
378 - mboxes
379 - shmem
387 - arm,scmi-smc
388 - arm,scmi-smc-param
389 - qcom,scmi-smc
392 - arm,smc-id
393 - shmem
400 const: linaro,scmi-optee
403 - linaro,optee-channel-id
406 - |
412 mbox-names = "tx", "rx";
416 #address-cells = <1>;
417 #size-cells = <0>;
419 atomic-threshold-us = <10000>;
423 #power-domain-cells = <1>;
428 #power-domain-cells = <1>;
432 mbox-names = "tx", "rx";
439 #clock-cells = <1>;
444 #thermal-sensor-cells = <1>;
449 #reset-cells = <1>;
455 #address-cells = <1>;
456 #size-cells = <0>;
460 regulator-max-microvolt = <3300000>;
465 regulator-min-microvolt = <500000>;
466 regulator-max-microvolt = <4200000>;
478 i2c2-pins {
483 mdio-pins {
485 drive-strength = <24>;
488 keys_pins: keys-pins {
490 bias-pull-up;
497 #address-cells = <2>;
498 #size-cells = <2>;
501 compatible = "mmio-sram";
504 #address-cells = <1>;
505 #size-cells = <1>;
508 cpu_scp_lpri0: scp-sram-section@0 {
509 compatible = "arm,scmi-shmem";
513 cpu_scp_lpri1: scp-sram-section@80 {
514 compatible = "arm,scmi-shmem";
518 cpu_scp_hpri0: scp-sram-section@100 {
519 compatible = "arm,scmi-shmem";
523 cpu_scp_hpri2: scp-sram-section@180 {
524 compatible = "arm,scmi-shmem";
530 - |
533 compatible = "arm,scmi-smc";
535 arm,smc-id = <0xc3000001>;
537 #address-cells = <1>;
538 #size-cells = <0>;
542 #power-domain-cells = <1>;
547 - |
550 compatible = "linaro,scmi-optee";
551 linaro,optee-channel-id = <0>;
553 #address-cells = <1>;
554 #size-cells = <0>;
558 linaro,optee-channel-id = <1>;
560 #power-domain-cells = <1>;
565 #clock-cells = <1>;
571 #address-cells = <2>;
572 #size-cells = <2>;
575 compatible = "mmio-sram";
578 #address-cells = <1>;
579 #size-cells = <1>;
582 cpu_optee_lpri0: optee-sram-section@0 {
583 compatible = "arm,scmi-shmem";