Lines Matching +full:fifo +full:- +full:width
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 described in "#dma-cells" property description below, using a three-cell
26 - Amelie Delaunay <[email protected]>
29 - $ref: /schemas/dma/dma-controller.yaml#
33 const: st,stm32mp25-dma3
42 Should contain all of the per-channel DMA interrupts in ascending order
51 power-domains:
54 "#dma-cells":
60 The second cell is a 32-bit mask specifying the DMA channel requirements:
61 -bit 0-1: The priority level
66 -bit 4-7: The FIFO requirement for queuing source/destination transfers
67 0x0: no FIFO requirement/any channel can fit
68 0x2: FIFO of 8 bytes (2^2+1)
69 0x4: FIFO of 32 bytes (2^4+1)
70 0x6: FIFO of 128 bytes (2^6+1)
71 0x7: FIFO of 256 bytes (2^7+1)
72 The third cell is a 32-bit mask specifying the DMA transfer requirements:
73 -bit 0: The source incrementing burst
76 -bit 1: The source allocated port
79 -bit 4: The destination incrementing burst
82 -bit 5: The destination allocated port
85 -bit 8: The type of hardware request
88 -bit 9: The control mode
91 -bit 12-13: The transfer complete event mode
99 -bit 16: Prevent packing/unpacking mode
100 0x0: pack/unpack enabled when source data width/burst != destination data width/burst
101 0x1: memory data width/burst forced to peripheral data width/burst to prevent pack/unpack
102 -bit 17: Prevent additional transfers due to linked-list refactoring
107 - compatible
108 - reg
109 - interrupts
110 - clocks
111 - "#dma-cells"
116 - |
117 #include <dt-bindings/interrupt-controller/arm-gic.h>
118 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
119 dma-controller@40400000 {
120 compatible = "st,stm32mp25-dma3";
139 #dma-cells = <3>;