Lines Matching +full:gcc +full:- +full:sm8250
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <[email protected]>
12 $ref: /schemas/display/msm/dpu-common.yaml#
17 - qcom,sm8150-dpu
18 - qcom,sm8250-dpu
22 - description: Address offset and size for mdp register set
23 - description: Address offset and size for vbif register set
25 reg-names:
27 - const: mdp
28 - const: vbif
32 - description: Display ahb clock
33 - description: Display hf axi clock
34 - description: Display core clock
35 - description: Display vsync clock
37 clock-names:
39 - const: iface
40 - const: bus
41 - const: core
42 - const: vsync
47 - |
48 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
49 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/interconnect/qcom,sm8150.h>
52 #include <dt-bindings/power/qcom-rpmpd.h>
54 display-controller@ae01000 {
55 compatible = "qcom,sm8150-dpu";
58 reg-names = "mdp", "vbif";
61 <&gcc GCC_DISP_HF_AXI_CLK>,
64 clock-names = "iface", "bus", "core", "vsync";
66 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
67 assigned-clock-rates = <19200000>;
69 operating-points-v2 = <&mdp_opp_table>;
70 power-domains = <&rpmhpd SM8150_MMCX>;
72 interrupt-parent = <&mdss>;
76 #address-cells = <1>;
77 #size-cells = <0>;
82 remote-endpoint = <&dsi0_in>;
89 remote-endpoint = <&dsi1_in>;