Lines Matching +full:mdss +full:- +full:dsi +full:- +full:ctrl
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6150 Display MDSS
10 - Abhinav Kumar <[email protected]>
11 - Dmitry Baryshkov <[email protected]>
14 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
15 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
16 bindings of MDSS are mentioned for SM6150 target.
18 $ref: /schemas/display/msm/mdss-common.yaml#
23 - const: qcom,sm6150-mdss
27 - description: Display AHB clock from gcc
28 - description: Display hf axi clock
29 - description: Display core clock
31 clock-names:
33 - const: iface
34 - const: bus
35 - const: core
43 interconnect-names:
47 "^display-controller@[0-9a-f]+$":
52 const: qcom,sm6150-dpu
54 "^dsi@[0-9a-f]+$":
60 - const: qcom,sm6150-dsi-ctrl
61 - const: qcom,mdss-dsi-ctrl
63 "^phy@[0-9a-f]+$":
68 const: qcom,sm6150-dsi-phy-14nm
73 - |
74 #include <dt-bindings/clock/qcom,rpmh.h>
75 #include <dt-bindings/interconnect/qcom,icc.h>
76 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
77 #include <dt-bindings/interrupt-controller/arm-gic.h>
78 #include <dt-bindings/power/qcom,rpmhpd.h>
80 display-subsystem@ae00000 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "qcom,sm6150-mdss";
85 reg-names = "mdss";
91 interconnect-names = "mdp0-mem", "cpu-cfg";
93 power-domains = <&dispcc_mdss_gdsc>;
100 interrupt-controller;
101 #interrupt-cells = <1>;
107 display-controller@ae01000 {
108 compatible = "qcom,sm6150-dpu";
111 reg-names = "mdp", "vbif";
117 clock-names = "iface", "bus", "core", "vsync";
119 assigned-clocks = <&dispcc_mdss_vsync_clk>;
120 assigned-clock-rates = <19200000>;
122 operating-points-v2 = <&mdp_opp_table>;
123 power-domains = <&rpmhpd RPMHPD_CX>;
125 interrupt-parent = <&mdss>;
129 #address-cells = <1>;
130 #size-cells = <0>;
141 remote-endpoint = <&mdss_dsi0_in>;
146 mdp_opp_table: opp-table {
147 compatible = "operating-points-v2";
149 opp-19200000 {
150 opp-hz = /bits/ 64 <19200000>;
151 required-opps = <&rpmhpd_opp_low_svs>;
154 opp-25600000 {
155 opp-hz = /bits/ 64 <25600000>;
156 required-opps = <&rpmhpd_opp_svs>;
159 opp-307200000 {
160 opp-hz = /bits/ 64 <307200000>;
161 required-opps = <&rpmhpd_opp_nom>;
166 dsi@ae94000 {
167 compatible = "qcom,sm6150-dsi-ctrl",
168 "qcom,mdss-dsi-ctrl";
170 reg-names = "dsi_ctrl";
172 interrupt-parent = <&mdss>;
181 clock-names = "byte",
188 assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
190 assigned-clock-parents = <&mdss_dsi0_phy 0>,
193 operating-points-v2 = <&dsi0_opp_table>;
197 #address-cells = <1>;
198 #size-cells = <0>;
201 #address-cells = <1>;
202 #size-cells = <0>;
207 remote-endpoint = <&dpu_intf1_out>;
218 dsi0_opp_table: opp-table {
219 compatible = "operating-points-v2";
221 opp-164000000 {
222 opp-hz = /bits/ 64 <164000000>;
223 required-opps = <&rpmhpd_opp_low_svs>;
229 compatible = "qcom,sm6150-dsi-phy-14nm";
233 reg-names = "dsi_phy",
237 #clock-cells = <1>;
238 #phy-cells = <0>;
242 clock-names = "iface", "ref";