Lines Matching +full:display +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SA87755P Display MDSS
10 - Mahadevan <[email protected]>
13 SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces and EDP etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sa8775p-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
34 interconnect-names:
38 "^display-controller@[0-9a-f]+$":
44 const: qcom,sa8775p-dpu
46 "^displayport-controller@[0-9a-f]+$":
53 - const: qcom,sa8775p-dp
56 - compatible
61 - |
62 #include <dt-bindings/interconnect/qcom,icc.h>
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
64 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
65 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
66 #include <dt-bindings/power/qcom,rpmhpd.h>
67 #include <dt-bindings/power/qcom-rpmpd.h>
69 display-subsystem@ae00000 {
70 compatible = "qcom,sa8775p-mdss";
72 reg-names = "mdss";
77 interconnect-names = "mdp0-mem",
78 "mdp1-mem",
79 "cpu-cfg";
82 power-domains = <&dispcc_gdsc>;
89 interrupt-controller;
90 #interrupt-cells = <1>;
94 #address-cells = <1>;
95 #size-cells = <1>;
98 display-controller@ae01000 {
99 compatible = "qcom,sa8775p-dpu";
102 reg-names = "mdp", "vbif";
109 clock-names = "nrt_bus",
115 assigned-clocks = <&dispcc_mdp_vsync_clk>;
116 assigned-clock-rates = <19200000>;
118 operating-points-v2 = <&mdss0_mdp_opp_table>;
119 power-domains = <&rpmhpd RPMHPD_MMCX>;
121 interrupt-parent = <&mdss0>;
125 #address-cells = <1>;
126 #size-cells = <0>;
131 remote-endpoint = <&mdss0_dp0_in>;
136 mdss0_mdp_opp_table: opp-table {
137 compatible = "operating-points-v2";
139 opp-375000000 {
140 opp-hz = /bits/ 64 <375000000>;
141 required-opps = <&rpmhpd_opp_svs_l1>;
144 opp-500000000 {
145 opp-hz = /bits/ 64 <500000000>;
146 required-opps = <&rpmhpd_opp_nom>;
149 opp-575000000 {
150 opp-hz = /bits/ 64 <575000000>;
151 required-opps = <&rpmhpd_opp_turbo>;
154 opp-650000000 {
155 opp-hz = /bits/ 64 <650000000>;
156 required-opps = <&rpmhpd_opp_turbo_l1>;
161 displayport-controller@af54000 {
162 compatible = "qcom,sa8775p-dp";
164 pinctrl-0 = <&dp_hot_plug_det>;
165 pinctrl-names = "default";
173 interrupt-parent = <&mdss0>;
181 clock-names = "core_iface",
187 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
189 assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;
192 phy-names = "dp";
194 operating-points-v2 = <&dp_opp_table>;
195 power-domains = <&rpmhpd SA8775P_MMCX>;
197 #sound-dai-cells = <0>;
200 #address-cells = <1>;
201 #size-cells = <0>;
206 remote-endpoint = <&dpu_intf0_out>;
216 dp_opp_table: opp-table {
217 compatible = "operating-points-v2";
219 opp-160000000 {
220 opp-hz = /bits/ 64 <160000000>;
221 required-opps = <&rpmhpd_opp_low_svs>;
224 opp-270000000 {
225 opp-hz = /bits/ 64 <270000000>;
226 required-opps = <&rpmhpd_opp_svs>;
229 opp-540000000 {
230 opp-hz = /bits/ 64 <540000000>;
231 required-opps = <&rpmhpd_opp_svs_l1>;
234 opp-810000000 {
235 opp-hz = /bits/ 64 <810000000>;
236 required-opps = <&rpmhpd_opp_nom>;