Lines Matching +full:display +full:- +full:hub
1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Rob Clark <[email protected]>
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - items:
24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
26 - items:
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28 - const: qcom,adreno-gmu
29 - const: qcom,adreno-gmu-wrapper
35 reg-names:
43 clock-names:
49 - description: GMU HFI interrupt
50 - description: GMU interrupt
52 interrupt-names:
54 - const: hfi
55 - const: gmu
57 power-domains:
59 - description: CX power domain
60 - description: GX power domain
62 power-domain-names:
64 - const: cx
65 - const: gx
72 description: Reference to the AOSS side-channel message RAM
74 operating-points-v2: true
76 opp-table:
80 - compatible
81 - reg
82 - reg-names
83 - power-domains
84 - power-domain-names
89 - if:
94 - qcom,adreno-gmu-618.0
95 - qcom,adreno-gmu-630.2
100 - description: Core GMU registers
101 - description: GMU PDC registers
102 - description: GMU PDC sequence registers
103 reg-names:
105 - const: gmu
106 - const: gmu_pdc
107 - const: gmu_pdc_seq
110 - description: GMU clock
111 - description: GPU CX clock
112 - description: GPU AXI clock
113 - description: GPU MEMNOC clock
114 clock-names:
116 - const: gmu
117 - const: cxo
118 - const: axi
119 - const: memnoc
121 - if:
126 - qcom,adreno-gmu-635.0
127 - qcom,adreno-gmu-660.1
128 - qcom,adreno-gmu-663.0
133 - description: Core GMU registers
134 - description: Resource controller registers
135 - description: GMU PDC registers
136 reg-names:
138 - const: gmu
139 - const: rscc
140 - const: gmu_pdc
143 - description: GMU clock
144 - description: GPU CX clock
145 - description: GPU AXI clock
146 - description: GPU MEMNOC clock
147 - description: GPU AHB clock
148 - description: GPU HUB CX clock
149 - description: GPU SMMU vote clock
150 clock-names:
152 - const: gmu
153 - const: cxo
154 - const: axi
155 - const: memnoc
156 - const: ahb
157 - const: hub
158 - const: smmu_vote
160 - if:
165 - qcom,adreno-gmu-640.1
170 - description: Core GMU registers
171 - description: GMU PDC registers
172 - description: GMU PDC sequence registers
173 reg-names:
175 - const: gmu
176 - const: gmu_pdc
177 - const: gmu_pdc_seq
179 - if:
184 - qcom,adreno-gmu-650.2
189 - description: Core GMU registers
190 - description: Resource controller registers
191 - description: GMU PDC registers
192 - description: GMU PDC sequence registers
193 reg-names:
195 - const: gmu
196 - const: rscc
197 - const: gmu_pdc
198 - const: gmu_pdc_seq
200 - if:
205 - qcom,adreno-gmu-640.1
206 - qcom,adreno-gmu-650.2
211 - description: GPU AHB clock
212 - description: GMU clock
213 - description: GPU CX clock
214 - description: GPU AXI clock
215 - description: GPU MEMNOC clock
216 clock-names:
218 - const: ahb
219 - const: gmu
220 - const: cxo
221 - const: axi
222 - const: memnoc
224 - if:
229 - qcom,adreno-gmu-730.1
230 - qcom,adreno-gmu-740.1
231 - qcom,adreno-gmu-750.1
232 - qcom,adreno-gmu-x185.1
237 - description: Core GMU registers
238 - description: Resource controller registers
239 - description: GMU PDC registers
240 reg-names:
242 - const: gmu
243 - const: rscc
244 - const: gmu_pdc
247 - description: GPU AHB clock
248 - description: GMU clock
249 - description: GPU CX clock
250 - description: GPU AXI clock
251 - description: GPU MEMNOC clock
252 - description: GMU HUB clock
253 - description: GPUSS DEMET clock
254 clock-names:
256 - const: ahb
257 - const: gmu
258 - const: cxo
259 - const: axi
260 - const: memnoc
261 - const: hub
262 - const: demet
265 - qcom,qmp
267 - if:
271 const: qcom,adreno-gmu-wrapper
276 - description: GMU wrapper register space
277 reg-names:
279 - const: gmu
282 - clocks
283 - clock-names
284 - interrupts
285 - interrupt-names
286 - iommus
287 - operating-points-v2
290 - |
291 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
292 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
293 #include <dt-bindings/interrupt-controller/irq.h>
294 #include <dt-bindings/interrupt-controller/arm-gic.h>
297 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
302 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
308 clock-names = "gmu", "cxo", "axi", "memnoc";
312 interrupt-names = "hfi", "gmu";
314 power-domains = <&gpucc GPU_CX_GDSC>,
316 power-domain-names = "cx", "gx";
319 operating-points-v2 = <&gmu_opp_table>;
323 compatible = "qcom,adreno-gmu-wrapper";
325 reg-names = "gmu";
326 power-domains = <&gpucc GPU_CX_GDSC>,
328 power-domain-names = "cx", "gx";