Lines Matching +full:mt8173 +full:- +full:gce

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <[email protected]>
11   - Philipp Zabel <[email protected]>
24       - enum:
25           - mediatek,mt8173-disp-split
26           - mediatek,mt8195-mdp3-split
27       - items:
28           - const: mediatek,mt6795-disp-split
29           - const: mediatek,mt8173-disp-split
37   power-domains:
40       Documentation/devicetree/bindings/power/power-domain.yaml for details.
43   mediatek,gce-client-reg:
45       The register of display function block to be set by gce. There are 4 arguments,
46       such as gce node, subsys id, offset and register size. The subsys id that is
47       mapping to the register of display function blocks is defined in the gce header
48       include/dt-bindings/gce/<chip>-gce.h of each chips.
49     $ref: /schemas/types.yaml#/definitions/phandle-array
52         - description: phandle of GCE
53         - description: GCE subsys id
54         - description: register offset
55         - description: register size
60       - description: SPLIT Clock
61       - description: Used for interfacing with the HDMI RX signal source.
62       - description: Paired with receiving HDMI RX metadata.
66   - compatible
67   - reg
68   - power-domains
69   - clocks
72   - if:
76             const: mediatek,mt8195-mdp3-split
84         - mediatek,gce-client-reg
86   - if:
90             const: mediatek,mt8173-disp-split
100   - |
101     #include <dt-bindings/clock/mt8173-clk.h>
102     #include <dt-bindings/power/mt8173-power.h>
105         #address-cells = <2>;
106         #size-cells = <2>;
109             compatible = "mediatek,mt8173-disp-split";
111             power-domains = <&spm MT8173_POWER_DOMAIN_MM>;