Lines Matching +full:mediatek +full:- +full:display
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display merge
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
14 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15 inputs into one side-by-side output.
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
24 - enum:
25 - mediatek,mt8173-disp-merge
26 - mediatek,mt8195-disp-merge
27 - mediatek,mt8195-mdp3-merge
28 - items:
29 - const: mediatek,mt6795-disp-merge
30 - const: mediatek,mt8173-disp-merge
31 - items:
32 - const: mediatek,mt8188-disp-merge
33 - const: mediatek,mt8195-disp-merge
41 power-domains:
44 Documentation/devicetree/bindings/power/power-domain.yaml for details.
50 clock-names:
52 - items:
53 - const: merge
54 - items:
55 - const: merge
56 - const: merge_async
58 mediatek,merge-fifo-en:
60 The setting of merge fifo is mainly provided for the display latency
61 buffer to ensure that the back-end panel display data will not be
68 mediatek,merge-mute:
72 mediatek,gce-client-reg:
76 defined in the header include/dt-bindings/gce/<chip>-gce.h.
77 $ref: /schemas/types.yaml#/definitions/phandle-array
84 connects to either the primary, secondary, etc, display pipeline.
100 - port@0
101 - port@1
109 - compatible
110 - reg
111 - power-domains
112 - clocks
117 - |
118 #include <dt-bindings/interrupt-controller/arm-gic.h>
119 #include <dt-bindings/clock/mt8173-clk.h>
120 #include <dt-bindings/power/mt8173-power.h>
123 #address-cells = <2>;
124 #size-cells = <2>;
127 compatible = "mediatek,mt8173-disp-merge";
129 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
131 clock-names = "merge";