Lines Matching +full:display +full:- +full:backend
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
15 designed for HDR video and graphics conversion in the external display path.
18 output the required HDR or SDR signal to the subsequent display path.
20 one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
21 These two function blocks read the pre-programmed registers from DRAM and
22 set them to HW in the v-blanking period.
27 - const: mediatek,mt8195-disp-ethdr
28 - items:
29 - const: mediatek,mt8188-disp-ethdr
30 - const: mediatek,mt8195-disp-ethdr
35 reg-names:
37 - const: mixer
38 - const: vdo_fe0
39 - const: vdo_fe1
40 - const: gfx_fe0
41 - const: gfx_fe1
42 - const: vdo_be
43 - const: adl_ds
54 - description: mixer clock
55 - description: video frontend 0 clock
56 - description: video frontend 1 clock
57 - description: graphic frontend 0 clock
58 - description: graphic frontend 1 clock
59 - description: video backend clock
60 - description: autodownload and menuload clock
61 - description: video frontend 0 async clock
62 - description: video frontend 1 async clock
63 - description: graphic frontend 0 async clock
64 - description: graphic frontend 1 async clock
65 - description: video backend async clock
66 - description: ethdr top clock
68 clock-names:
70 - const: mixer
71 - const: vdo_fe0
72 - const: vdo_fe1
73 - const: gfx_fe0
74 - const: gfx_fe1
75 - const: vdo_be
76 - const: adl_ds
77 - const: vdo_fe0_async
78 - const: vdo_fe1_async
79 - const: gfx_fe0_async
80 - const: gfx_fe1_async
81 - const: vdo_be_async
82 - const: ethdr_top
84 power-domains:
89 - description: video frontend 0 async reset
90 - description: video frontend 1 async reset
91 - description: graphic frontend 0 async reset
92 - description: graphic frontend 1 async reset
93 - description: video backend async reset
95 reset-names:
97 - const: vdo_fe0_async
98 - const: vdo_fe1_async
99 - const: gfx_fe0_async
100 - const: gfx_fe1_async
101 - const: vdo_be_async
103 mediatek,gce-client-reg:
104 $ref: /schemas/types.yaml#/definitions/phandle-array
107 description: The register of display function block to be set by gce.
110 include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
117 connects to either the primary, secondary, etc, display pipeline.
128 display pipeline, for example one of the available MERGE blocks,
132 - port@0
133 - port@1
136 - compatible
137 - reg
138 - clocks
139 - clock-names
140 - interrupts
141 - power-domains
142 - resets
143 - mediatek,gce-client-reg
148 - |
149 #include <dt-bindings/interrupt-controller/arm-gic.h>
150 #include <dt-bindings/clock/mt8195-clk.h>
151 #include <dt-bindings/gce/mt8195-gce.h>
152 #include <dt-bindings/memory/mt8195-memory-port.h>
153 #include <dt-bindings/power/mt8195-power.h>
154 #include <dt-bindings/reset/mt8195-resets.h>
157 #address-cells = <2>;
158 #size-cells = <2>;
160 hdr-engine@1c114000 {
161 compatible = "mediatek,mt8195-disp-ethdr";
169 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
171 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
191 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
195 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
204 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",