Lines Matching +full:mt8195 +full:- +full:disp +full:- +full:dsc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: mediatek display DSC controller
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
14 The DSC standard is a specification of the algorithms used for
17 video bit stream. DSC is designed for real-time systems with
18 real-time compression, transmission, decompression and Display.
23 - enum:
24 - mediatek,mt8195-disp-dsc
34 - description: DSC Wrapper Clock
36 power-domains:
39 Documentation/devicetree/bindings/power/power-domain.yaml for details.
41 mediatek,gce-client-reg:
48 include/dt-bindings/gce/<chip>-gce.h.
49 $ref: /schemas/types.yaml#/definitions/phandle-array
73 - port@0
74 - port@1
77 - compatible
78 - reg
79 - interrupts
80 - power-domains
81 - clocks
86 - |
87 #include <dt-bindings/interrupt-controller/arm-gic.h>
88 #include <dt-bindings/clock/mt8195-clk.h>
89 #include <dt-bindings/power/mt8195-power.h>
90 #include <dt-bindings/gce/mt8195-gce.h>
93 #address-cells = <2>;
94 #size-cells = <2>;
97 compatible = "mediatek,mt8195-disp-dsc";
100 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
102 mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;