Lines Matching +full:mt8195 +full:- +full:dp +full:- +full:tx
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <[email protected]>
11 - Jitao shi <[email protected]>
14 MediaTek DP and eDP are different hardwares and there are some features
17 In addition, We just need to enable the power domain of DP, so the clock
18 of DP is generated by itself and we are not using other PLL to generate
24 - mediatek,mt8188-dp-tx
25 - mediatek,mt8188-edp-tx
26 - mediatek,mt8195-dp-tx
27 - mediatek,mt8195-edp-tx
32 nvmem-cells:
36 nvmem-cell-names:
39 power-domains:
45 '#sound-dai-cells':
56 $ref: /schemas/graph.yaml#/$defs/port-base
61 $ref: /schemas/media/video-interfaces.yaml#
64 data-lanes:
68 0 - For 1 lane enabled in IP.
69 0 1 - For 2 lanes enabled in IP.
70 0 1 2 3 - For 4 lanes enabled in IP.
74 - data-lanes
77 - port@0
78 - port@1
80 max-linkrate-mhz:
85 - compatible
86 - reg
87 - interrupts
88 - ports
89 - max-linkrate-mhz
92 - $ref: /schemas/sound/dai-common.yaml#
93 - if:
99 - mediatek,mt8188-dp-tx
100 - mediatek,mt8195-dp-tx
103 '#sound-dai-cells': false
108 - |
109 #include <dt-bindings/interrupt-controller/arm-gic.h>
110 #include <dt-bindings/power/mt8195-power.h>
112 compatible = "mediatek,mt8195-dp-tx";
114 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
116 max-linkrate-mhz = <8100>;
119 #address-cells = <1>;
120 #size-cells = <0>;
125 remote-endpoint = <&dp_intf0_out>;
131 data-lanes = <0 1 2 3>;