Lines Matching +full:sec +full:- +full:v4
1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
4 -SEC 6 Node
5 -Job Ring Node
6 -Full Example
9 SEC 6 Node
13 Node defines the base address of the SEC 6 block.
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
20 - compatible
23 Definition: Must include "fsl,sec-v6.0".
25 - fsl,sec-era
28 Definition: A standard property. Define the 'ERA' of the SEC
31 - #address-cells
37 - #size-cells
44 - reg
46 Value type: <prop-encoded-array>
48 address and length of the SEC 6 configuration registers.
50 - ranges
52 Value type: <prop-encoded-array>
54 range of the SEC 6.0 register space (-SNVS not included). A
63 compatible = "fsl,sec-v6.0";
64 fsl,sec-era = <6>;
65 #address-cells = <1>;
66 #size-cells = <1>;
74 Child of the crypto node defines data processing interface to SEC 6
81 - compatible
84 Definition: Must include "fsl,sec-v6.0-job-ring".
86 - reg
88 Value type: <prop-encoded-array>
92 - interrupts
94 Value type: <prop_encoded-array>
103 compatible = "fsl,sec-v6.0-job-ring";
111 Since some chips may contain more than one SEC, the dtsi contains
112 only the node contents, not the node itself. A chip using the SEC
113 should include the dtsi inside each SEC node. Example:
115 In qoriq-sec6.0.dtsi:
117 compatible = "fsl,sec-v6.0";
118 fsl,sec-era = <6>;
119 #address-cells = <1>;
120 #size-cells = <1>;
123 compatible = "fsl,sec-v6.0-job-ring",
124 "fsl,sec-v5.2-job-ring",
125 "fsl,sec-v5.0-job-ring",
126 "fsl,sec-v4.4-job-ring",
127 "fsl,sec-v4.0-job-ring";
132 compatible = "fsl,sec-v6.0-job-ring",
133 "fsl,sec-v5.2-job-ring",
134 "fsl,sec-v5.0-job-ring",
135 "fsl,sec-v4.4-job-ring",
136 "fsl,sec-v4.0-job-ring";
143 /include/ "qoriq-sec6.0.dtsi"