Lines Matching +full:next +full:- +full:level +full:- +full:cache
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <[email protected]>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sc8180x-cpufreq-hw
27 - qcom,sdm670-cpufreq-hw
28 - qcom,sdm845-cpufreq-hw
29 - qcom,sm6115-cpufreq-hw
30 - qcom,sm6350-cpufreq-hw
31 - qcom,sm8150-cpufreq-hw
32 - const: qcom,cpufreq-hw
34 - description: v2 of CPUFREQ HW (EPSS)
36 - enum:
37 - qcom,qdu1000-cpufreq-epss
38 - qcom,sa8255p-cpufreq-epss
39 - qcom,sa8775p-cpufreq-epss
40 - qcom,sar2130p-cpufreq-epss
41 - qcom,sc7280-cpufreq-epss
42 - qcom,sc8280xp-cpufreq-epss
43 - qcom,sdx75-cpufreq-epss
44 - qcom,sm4450-cpufreq-epss
45 - qcom,sm6375-cpufreq-epss
46 - qcom,sm8250-cpufreq-epss
47 - qcom,sm8350-cpufreq-epss
48 - qcom,sm8450-cpufreq-epss
49 - qcom,sm8550-cpufreq-epss
50 - qcom,sm8650-cpufreq-epss
51 - const: qcom,cpufreq-epss
56 - description: Frequency domain 0 register region
57 - description: Frequency domain 1 register region
58 - description: Frequency domain 2 register region
59 - description: Frequency domain 3 register region
61 reg-names:
64 - const: freq-domain0
65 - const: freq-domain1
66 - const: freq-domain2
67 - const: freq-domain3
71 - description: XO Clock
72 - description: GPLL0 Clock
74 clock-names:
76 - const: xo
77 - const: alternate
83 interrupt-names:
86 - const: dcvsh-irq-0
87 - const: dcvsh-irq-1
88 - const: dcvsh-irq-2
89 - const: dcvsh-irq-3
91 '#freq-domain-cells':
94 '#clock-cells':
98 - compatible
99 - reg
100 - clocks
101 - clock-names
102 - '#freq-domain-cells'
107 - if:
112 - qcom,qcm2290-cpufreq-hw
113 - qcom,sar2130p-cpufreq-epss
120 reg-names:
128 interrupt-names:
131 - if:
136 - qcom,qdu1000-cpufreq-epss
137 - qcom,sa8255p-cpufreq-epss
138 - qcom,sc7180-cpufreq-hw
139 - qcom,sc8180x-cpufreq-hw
140 - qcom,sc8280xp-cpufreq-epss
141 - qcom,sdm670-cpufreq-hw
142 - qcom,sdm845-cpufreq-hw
143 - qcom,sm4450-cpufreq-epss
144 - qcom,sm6115-cpufreq-hw
145 - qcom,sm6350-cpufreq-hw
146 - qcom,sm6375-cpufreq-epss
153 reg-names:
161 interrupt-names:
164 - if:
169 - qcom,sc7280-cpufreq-epss
170 - qcom,sm8250-cpufreq-epss
171 - qcom,sm8350-cpufreq-epss
172 - qcom,sm8450-cpufreq-epss
173 - qcom,sm8550-cpufreq-epss
180 reg-names:
188 interrupt-names:
191 - if:
196 - qcom,sm8150-cpufreq-hw
203 reg-names:
212 interrupt-names:
217 - |
218 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
219 #include <dt-bindings/clock/qcom,rpmh.h>
221 // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
224 #address-cells = <2>;
225 #size-cells = <0>;
231 enable-method = "psci";
232 next-level-cache = <&L2_0>;
233 qcom,freq-domain = <&cpufreq_hw 0>;
235 L2_0: l2-cache {
236 compatible = "cache";
237 cache-unified;
238 cache-level = <2>;
239 next-level-cache = <&L3_0>;
240 L3_0: l3-cache {
241 compatible = "cache";
242 cache-unified;
243 cache-level = <3>;
252 enable-method = "psci";
253 next-level-cache = <&L2_100>;
254 qcom,freq-domain = <&cpufreq_hw 0>;
256 L2_100: l2-cache {
257 compatible = "cache";
258 cache-unified;
259 cache-level = <2>;
260 next-level-cache = <&L3_0>;
268 enable-method = "psci";
269 next-level-cache = <&L2_200>;
270 qcom,freq-domain = <&cpufreq_hw 0>;
272 L2_200: l2-cache {
273 compatible = "cache";
274 cache-unified;
275 cache-level = <2>;
276 next-level-cache = <&L3_0>;
284 enable-method = "psci";
285 next-level-cache = <&L2_300>;
286 qcom,freq-domain = <&cpufreq_hw 0>;
288 L2_300: l2-cache {
289 compatible = "cache";
290 cache-unified;
291 cache-level = <2>;
292 next-level-cache = <&L3_0>;
300 enable-method = "psci";
301 next-level-cache = <&L2_400>;
302 qcom,freq-domain = <&cpufreq_hw 1>;
304 L2_400: l2-cache {
305 compatible = "cache";
306 cache-unified;
307 cache-level = <2>;
308 next-level-cache = <&L3_0>;
316 enable-method = "psci";
317 next-level-cache = <&L2_500>;
318 qcom,freq-domain = <&cpufreq_hw 1>;
320 L2_500: l2-cache {
321 compatible = "cache";
322 cache-unified;
323 cache-level = <2>;
324 next-level-cache = <&L3_0>;
332 enable-method = "psci";
333 next-level-cache = <&L2_600>;
334 qcom,freq-domain = <&cpufreq_hw 1>;
336 L2_600: l2-cache {
337 compatible = "cache";
338 cache-unified;
339 cache-level = <2>;
340 next-level-cache = <&L3_0>;
348 enable-method = "psci";
349 next-level-cache = <&L2_700>;
350 qcom,freq-domain = <&cpufreq_hw 1>;
352 L2_700: l2-cache {
353 compatible = "cache";
354 cache-unified;
355 cache-level = <2>;
356 next-level-cache = <&L3_0>;
362 #address-cells = <1>;
363 #size-cells = <1>;
366 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
368 reg-names = "freq-domain0", "freq-domain1";
371 clock-names = "xo", "alternate";
373 #freq-domain-cells = <1>;
374 #clock-cells = <1>;