Lines Matching +full:zynq +full:- +full:gpio +full:- +full:1

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 title: LogicoreIP designed compatible with Xilinx ZYNQ family.
9   - Rohit Visavalia <[email protected]>
19       - enum:
20           - xlnx,vcu
21           - xlnx,vcu-logicoreip-1.0
24     maxItems: 1
28       - description: pll ref clocksource
29       - description: aclk
31   clock-names:
33       - const: pll_ref
34       - const: aclk
36   reset-gpios:
37     maxItems: 1
40   - reg
41   - clocks
42   - clock-names
47   - |
48     #include <dt-bindings/gpio/gpio.h>
50         #address-cells = <2>;
51         #size-cells = <2>;
53             compatible = "xlnx,vcu-logicoreip-1.0";
55             reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
57             clock-names = "pll_ref", "aclk";