Lines Matching +full:versal +full:- +full:fpga
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <[email protected]>
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
23 - xlnx,versal-clk-wizard
29 "#clock-cells":
34 - description: clock input
35 - description: axi clock
37 clock-names:
39 - const: clk_in1
40 - const: s_axi_aclk
42 xlnx,static-config:
48 xlnx,speed-grade:
52 Speed grade of the device. Higher the speed grade faster is the FPGA device.
54 xlnx,nr-outputs:
62 - compatible
63 - reg
64 - "#clock-cells"
65 - clocks
66 - clock-names
67 - xlnx,speed-grade
68 - xlnx,nr-outputs
73 - |
74 clock-controller@b0000000 {
75 compatible = "xlnx,clocking-wizard";
77 #clock-cells = <1>;
78 xlnx,static-config;
79 xlnx,speed-grade = <1>;
80 xlnx,nr-outputs = <6>;
81 clock-names = "clk_in1", "s_axi_aclk";