Lines Matching +full:stm32h743 +full:- +full:rcc

4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11   "st,stm32h743-rcc"
13 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
18 - #clock-cells : from common clock binding; shall be set to 1
20 - clocks: External oscillator clock phandle
21   - high speed external clock signal (HSE)
22   - low speed external clock signal (LSE)
23   - external I2S clock (I2S_CKIN)
26 - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
31 	rcc: reset-clock-controller@58024400 {
32 		compatible = "st,stm32h743-rcc", "st,stm32-rcc";
34 		#reset-cells = <1>;
35 		#clock-cells = <1>;
47 			compatible = "st,stm32-timer";
50 			clocks = <&rcc TIM5_CK>;
59 The index is the bit number within the RCC registers bank, starting from RCC
70 		resets	= <&rcc STM32H7_APB1L_RESET(TIM2)>;