Lines Matching +full:clock +full:- +full:tree
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos990 SoC clock controller
10 - Igor Belwon <[email protected]>
11 - Chanwoo Choi <[email protected]>
12 - Krzysztof Kozlowski <[email protected]>
15 Exynos990 clock controller is comprised of several CMU units, generating
17 tree nodes, and might depend on each other. The root clock in that root tree
18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
19 as a fixed-rate clock in dts.
21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 Each clock is assigned an identifier and client nodes can use this identifier
26 to specify the clock which they consume. All clocks available for usage
27 in clock consumer nodes are defined as preprocessor macros in
28 'include/dt-bindings/clock/samsung,exynos990.h' header.
33 - samsung,exynos990-cmu-hsi0
34 - samsung,exynos990-cmu-top
40 clock-names:
44 "#clock-cells":
51 - compatible
52 - clocks
53 - clock-names
54 - "#clock-cells"
55 - reg
58 - if:
62 const: samsung,exynos990-cmu-hsi0
68 - description: External reference clock (26 MHz)
69 - description: CMU_HSI0 BUS clock (from CMU_TOP)
70 - description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
71 - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
72 - description: CMU_HSI0 DPGTC clock (from CMU_TOP)
74 clock-names:
76 - const: oscclk
77 - const: bus
78 - const: usb31drd
79 - const: usbdp_debug
80 - const: dpgtc
82 - if:
86 const: samsung,exynos990-cmu-top
92 - description: External reference clock (26 MHz)
94 clock-names:
96 - const: oscclk
101 - |
102 #include <dt-bindings/clock/samsung,exynos990.h>
104 cmu_hsi0: clock-controller@10a00000 {
105 compatible = "samsung,exynos990-cmu-hsi0";
107 #clock-cells = <1>;
114 clock-names = "oscclk",