Lines Matching +full:clock +full:- +full:specifier
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
10 - Lad Prabhakar <prabhakar.mahadev-[email protected]>
13 On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
14 generation and control of clock signals for the IP modules, generation and
21 - renesas,r9a09g047-cpg # RZ/G3E
22 - renesas,r9a09g057-cpg # RZ/V2H
29 - description: AUDIO_EXTAL clock input
30 - description: RTXIN clock input
31 - description: QEXTAL clock input
33 clock-names:
35 - const: audio_extal
36 - const: rtxin
37 - const: qextal
39 '#clock-cells':
41 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
42 and a core clock reference, as defined in
43 <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
44 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
51 '#power-domain-cells':
54 '#reset-cells':
56 The single reset specifier cell must be the reset number. The reset number
63 - compatible
64 - reg
65 - clocks
66 - clock-names
67 - '#clock-cells'
68 - '#power-domain-cells'
69 - '#reset-cells'
74 - |
75 clock-controller@10420000 {
76 compatible = "renesas,r9a09g057-cpg";
79 clock-names = "audio_extal", "rtxin", "qextal";
80 #clock-cells = <2>;
81 #power-domain-cells = <0>;
82 #reset-cells = <1>;