Lines Matching +full:sa8775p +full:- +full:gcc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SA8775P
10 - Taniya Das <[email protected]>
14 domains on SA8775P.
16 See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
21 - qcom,sa8775p-dispcc0
22 - qcom,sa8775p-dispcc1
26 - description: GCC AHB clock source
27 - description: Board XO source
28 - description: Board XO_AO source
29 - description: Sleep clock source
30 - description: Link clock from DP0 PHY
31 - description: VCO DIV clock from DP0 PHY
32 - description: Link clock from DP1 PHY
33 - description: VCO DIV clock from DP1 PHY
34 - description: Byte clock from DSI0 PHY
35 - description: Pixel clock from DSI0 PHY
36 - description: Byte clock from DSI1 PHY
37 - description: Pixel clock from DSI1 PHY
39 power-domains:
44 - compatible
45 - clocks
46 - power-domains
47 - '#power-domain-cells'
50 - $ref: qcom,gcc.yaml#
55 - |
56 #include <dt-bindings/clock/qcom,rpmh.h>
57 #include <dt-bindings/power/qcom-rpmpd.h>
58 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
59 clock-controller@af00000 {
60 compatible = "qcom,sa8775p-dispcc0";
62 clocks = <&gcc GCC_DISP_AHB_CLK>,
74 power-domains = <&rpmhpd SA8775P_MMCX>;
75 #clock-cells = <1>;
76 #reset-cells = <1>;
77 #power-domain-cells = <1>;