Lines Matching +full:assigned +full:- +full:clock +full:- +full:rates +full:- +full:u64
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm CMN PLL Clock Controller on IPQ SoC
10 - Bjorn Andersson <[email protected]>
11 - Luo Jie <[email protected]>
14 The CMN (or common) PLL clock controller expects a reference
15 input clock. This reference clock is from the on-board Wi-Fi.
27 - qcom,ipq9574-cmn-pll
34 - description: The reference clock. The supported clock rates include
36 - description: The AHB clock
37 - description: The SYS clock
39 The reference clock is the source clock of CMN PLL, which is from the
40 Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
41 clock registers.
43 clock-names:
45 - const: ref
46 - const: ahb
47 - const: sys
49 "#clock-cells":
53 - compatible
54 - reg
55 - clocks
56 - clock-names
57 - "#clock-cells"
62 - |
63 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
64 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
66 cmn_pll: clock-controller@9b000 {
67 compatible = "qcom,ipq9574-cmn-pll";
72 clock-names = "ref", "ahb", "sys";
73 #clock-cells = <1>;
74 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
75 assigned-clock-rates-u64 = /bits/ 64 <12000000000>;