Lines Matching +full:sata +full:- +full:port
12 -----------------------------------
20 15 sata0 SATA Host 0
25 30 sata1 SATA Host 0
29 -----------------------------------
37 14 sata0_link SATA 0 Link
38 15 sata0_core SATA 0 Core
43 20 sata1_link SATA 1 Link
44 21 sata1_core SATA 1 Core
49 28 crypto0_enc Cryptographic Unit Port 0 Encryption
50 29 crypto0_core Cryptographic Unit Port 0 Core
51 30 crypto1_enc Cryptographic Unit Port 1 Encryption
52 31 crypto1_core Cryptographic Unit Port 1 Core
56 -----------------------------------
70 15 sata0 SATA 0
79 30 sata1 SATA 1
83 -----------------------------------
90 15 sata0 SATA 0
97 -----------------------------------
109 15 sata0 SATA Host 0
120 30 sata1 SATA Host 1
124 -----------------------------------
134 -----------------------------------
138 3 sata SATA Host
157 -----------------------------------
167 14 sata0 SATA Host 0
168 15 sata1 SATA Host 1
176 - compatible : shall be one of the following:
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
186 - #clock-cells : from common clock binding; shall be set to 1
189 - clocks : default parent clock phandle (e.g. tclk)
193 gate_clk: clock-gating-control@d0038 {
194 compatible = "marvell,dove-gating-clock";
198 #clock-cells = <1>;
202 compatible = "marvell,dove-sdhci";