Lines Matching +full:xo +full:- +full:clk +full:- +full:gpios
5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
14 - compatible: "maxim,max9485"
15 - clocks: Input clock, must provide 27.000 MHz
16 - clock-names: Must be set to "xclk"
17 - #clock-cells: From common clock binding; shall be set to 1
20 - reset-gpios: GPIO descriptor connected to the #RESET input pin
21 - vdd-supply: A regulator node for Vdd
22 - clock-output-names: Name of output clocks, as defined in common clock
28 Clocks are defined as preprocessor macros in the dt-binding header.
32 #include <dt-bindings/clock/maxim,max9485.h>
34 xo-27mhz: xo-27mhz {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <27000000>;
41 max9485: audio-clock@63 {
44 clock-names = "xclk";
45 clocks = <&xo-27mhz>;
46 reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
47 vdd-supply = <&3v3-reg>;
48 #clock-cells = <1>;
57 clock-names = "foo-input-clk";