Lines Matching +full:tegra194 +full:- +full:cbb +full:- +full:noc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 CBB 1.0
10 - Sumit Gupta <[email protected]>
13 The Control Backbone (CBB) is comprised of the physical path from an
14 initiator to a target's register configuration space. CBB 1.0 has
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
19 by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
21 which is the main NOC.
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
35 engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
44 pattern: "^[a-z]+-noc@[0-9a-f]+$"
48 - nvidia,tegra194-cbb-noc
49 - nvidia,tegra194-aon-noc
50 - nvidia,tegra194-bpmp-noc
51 - nvidia,tegra194-rce-noc
52 - nvidia,tegra194-sce-noc
61 non-secure interrupt is received for TMO & DEC errors.
63 - description: non-secure interrupt
64 - description: secure interrupt
81 - compatible
82 - reg
83 - interrupts
84 - nvidia,apbmisc
87 - |
88 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 cbb-noc@2300000 {
91 compatible = "nvidia,tegra194-cbb-noc";