Lines Matching +full:max +full:- +full:memory +full:- +full:bandwidth
1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Fenghua Yu <[email protected]>
10 - Tony Luck <[email protected]>
11 - Vikas Shivappa <[email protected]>
25 MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
26 MBA (Memory Bandwidth Allocation) "mba"
27 SMBA (Slow Memory Bandwidth Allocation) ""
28 BMEC (Bandwidth Monitoring Event Configuration) ""
38 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl
48 bandwidth in MiBps
57 pseudo-locking is a unique way of using cache control to "pin" or
59 "Cache Pseudo-Locking".
96 own settings for cache use which can over-ride
128 Corresponding region is pseudo-locked. No
131 Indicates if non-contiguous 1s value in CBM is supported.
136 Non-contiguous 1s value in CBM is supported.
138 Memory bandwidth(MB) subdirectory contains the following files
142 The minimum memory bandwidth percentage which
146 The granularity in which the memory bandwidth
150 available bandwidth control steps are:
155 non-linear. This field is purely informational
161 request different memory bandwidth percentages:
163 "max":
166 "per-thread":
167 bandwidth percentages are directly applied to
188 If the system supports Bandwidth Monitoring Event
189 Configuration (BMEC), then the bandwidth events will
201 and mbm_local_bytes events, respectively, when the Bandwidth
205 changed, the bandwidth counters for all RMIDs of both events
215 6 Dirty Victims from the QOS domain to all types of memory
216 5 Reads to slow memory in the non-local NUMA domain
217 4 Reads to slow memory in the local NUMA domain
218 3 Non-temporal writes to non-local NUMA domain
219 2 Non-temporal writes to local NUMA domain
220 1 Reads to memory in the non-local NUMA domain
221 0 Reads to memory in the local NUMA domain
226 0x15 to count all the local memory events.
249 * To change the mbm_local_bytes to count all the slow memory reads on
262 counter can be considered for re-use.
275 mask f7 has non-consecutive 1-bits
332 When the resource group is in pseudo-locked mode this file will
334 pseudo-locked region.
345 Each resource has its own line and format - see below for details.
356 cache pseudo-locked region is created by first writing
357 "pseudo-locksetup" to the "mode" file before writing the cache
358 pseudo-locked region's schemata to the resource group's "schemata"
359 file. On successful pseudo-locked region creation the mode will
360 automatically change to "pseudo-locked".
378 On systems with Sub-NUMA Cluster (SNC) enabled there are extra
390 Reading this file shows which memory bandwidth event is used
391 as input to the software feedback loop that keeps memory bandwidth
393 name of one of the supported memory bandwidth events found in
398 -------------------------
403 1) If the task is a member of a non-default group, then the schemata
413 -------------------------
414 1) If a task is a member of a MON group, or non-default CTRL_MON group
435 are evicted and re-used while the occupancy in the new group rises as
436 the task accesses memory and loads into the cache are counted based on
450 max_threshold_occupancy - generic concepts
451 ------------------------------------------
457 limbo RMIDs but which are not ready to be used, user may see an -EBUSY
469 Schemata files - general concepts
470 ---------------------------------
476 ---------
488 ---------------------
495 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9
497 if non-contiguous 1s value is supported. On a system with a 20-bit mask
501 Notes on Sub-NUMA Cluster mode
503 When SNC mode is enabled, Linux may load balance tasks between Sub-NUMA
505 on Sub-NUMA nodes share the same L3 cache and the system may report
506 the NUMA distance between Sub-NUMA nodes with a lower value than used
509 The top-level monitoring files in each "mon_L3_XX" directory provide
511 Users who bind tasks to the CPUs of a specific Sub-NUMA node can read
515 Memory bandwidth allocation is still performed at the L3 cache
520 of SNC nodes per L3 cache. E.g. with a 100MB cache on a system with 10-bit
524 Memory bandwidth Allocation and monitoring
527 For Memory bandwidth resource, by default the user controls the resource
528 by indicating the percentage of total memory bandwidth.
530 The minimum bandwidth percentage value for each cpu model is predefined
531 and can be looked up through "info/MB/min_bandwidth". The bandwidth
533 be looked up at "info/MB/bandwidth_gran". The available bandwidth
537 The bandwidth throttling is a core specific mechanism on some of Intel
538 SKUs. Using a high bandwidth and a low bandwidth setting on two threads
540 low bandwidth (see "thread_throttle_mode").
542 The fact that Memory bandwidth allocation(MBA) may be a core
543 specific mechanism where as memory bandwidth monitoring(MBM) is done at
545 via the MBA and then monitor the bandwidth to see if the controls are
548 1. User may *not* see increase in actual bandwidth when percentage
551 This can occur when aggregate L2 external bandwidth is more than L3
552 external bandwidth. Consider an SKL SKU with 24 cores on a package and
553 where L2 external is 10GBps (hence aggregate L2 external bandwidth is
554 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
555 threads, having 50% bandwidth, each consuming 5GBps' consumes the max L3
556 bandwidth of 100GBps although the percentage value specified is only 50%
557 << 100%. Hence increasing the bandwidth percentage will not yield any
558 more bandwidth. This is because although the L2 external bandwidth still
559 has capacity, the L3 external bandwidth is fully used. Also note that
562 2. Same bandwidth percentage may mean different actual bandwidth
565 For the same SKU in #1, a 'single thread, with 10% bandwidth' and '4
566 thread, with 10% bandwidth' can consume upto 10GBps and 40GBps although
567 they have same percentage bandwidth of 10%. This is simply because as
568 threads start using more cores in an rdtgroup, the actual bandwidth may
569 increase or vary although user specified bandwidth percentage is same.
572 resctrl added support for specifying the bandwidth in MiBps as well. The
574 Controller(mba_sc)" which reads the actual bandwidth using MBM counters
575 and adjust the memory bandwidth percentages to ensure::
577 "actual bandwidth < user specified bandwidth".
579 By default, the schemata would take the bandwidth percentage values
585 ----------------------------------------------------------------
591 ------------------------------------------------------------------
599 ------------------------
611 Memory bandwidth Allocation (default mode)
612 ------------------------------------------
614 Memory b/w domain is L3 cache.
619 Memory bandwidth Allocation specified in MiBps
620 ----------------------------------------------
622 Memory bandwidth domain is L3 cache.
627 Slow Memory Bandwidth Allocation (SMBA)
628 ---------------------------------------
629 AMD hardware supports Slow Memory Bandwidth Allocation (SMBA).
630 CXL.memory is the only supported "slow" memory device. With the
631 support of SMBA, the hardware enables bandwidth allocation on
632 the slow memory devices. If there are multiple such devices in
636 The presence of SMBA (with CXL.memory) is independent of slow memory
640 The bandwidth domain for slow memory is L3 cache. Its schemata file
647 ---------------------------------
662 --------------------------------------------------
663 Reading the schemata file will show the current bandwidth limit on all
666 configure the bandwidth limit.
682 --------------------------------------------------------------------
701 Cache Pseudo-Locking
704 application can fill. Cache pseudo-locking builds on the fact that a
705 CPU can still read and write data pre-allocated outside its current
706 allocated area on a cache hit. With cache pseudo-locking, data can be
709 pseudo-locked memory is made accessible to user space where an
711 a region of memory with reduced average read latency.
713 The creation of a cache pseudo-locked region is triggered by a request
715 to be pseudo-locked. The cache pseudo-locked region is created as follows:
717 - Create a CAT allocation CLOSNEW with a CBM matching the schemata
718 from the user of the cache region that will contain the pseudo-locked
719 memory. This region must not overlap with any current CAT allocation/CLOS
721 while the pseudo-locked region exists.
722 - Create a contiguous region of memory of the same size as the cache
724 - Flush the cache, disable hardware prefetchers, disable preemption.
725 - Make CLOSNEW the active CLOS and touch the allocated memory to load
727 - Set the previous CLOS as active.
728 - At this point the closid CLOSNEW can be released - the cache
729 pseudo-locked region is protected as long as its CBM does not appear in
730 any CAT allocation. Even though the cache pseudo-locked region will from
732 any CLOS will be able to access the memory in the pseudo-locked region since
734 - The contiguous region of memory loaded into the cache is exposed to
735 user-space as a character device.
737 Cache pseudo-locking increases the probability that data will remain
741 “locked” data from cache. Power management C-states may shrink or
742 power off cache. Deeper C-states will automatically be restricted on
743 pseudo-locked region creation.
745 It is required that an application using a pseudo-locked region runs
747 with the cache on which the pseudo-locked region resides. A sanity check
748 within the code will not allow an application to map pseudo-locked memory
750 pseudo-locked region resides. The sanity check is only done during the
754 Pseudo-locking is accomplished in two stages:
757 of cache that should be dedicated to pseudo-locking. At this time an
758 equivalent portion of memory is allocated, loaded into allocated
760 2) During the second stage a user-space application maps (mmap()) the
761 pseudo-locked memory into its address space.
763 Cache Pseudo-Locking Interface
764 ------------------------------
765 A pseudo-locked region is created using the resctrl interface as follows:
768 2) Change the new resource group's mode to "pseudo-locksetup" by writing
769 "pseudo-locksetup" to the "mode" file.
770 3) Write the schemata of the pseudo-locked region to the "schemata" file. All
774 On successful pseudo-locked region creation the "mode" file will contain
775 "pseudo-locked" and a new character device with the same name as the resource
777 by user space in order to obtain access to the pseudo-locked memory region.
779 An example of cache pseudo-locked region creation and usage can be found below.
781 Cache Pseudo-Locking Debugging Interface
782 ----------------------------------------
783 The pseudo-locking debugging interface is enabled by default (if
786 There is no explicit way for the kernel to test if a provided memory
787 location is present in the cache. The pseudo-locking debugging interface uses
789 the pseudo-locked region:
791 1) Memory access latency using the pseudo_lock_mem_latency tracepoint. Data
793 example below). In this test the pseudo-locked region is traversed at
801 When a pseudo-locked region is created a new debugfs directory is created for
803 write-only file, pseudo_lock_measure, is present in this directory. The
804 measurement of the pseudo-locked region depends on the number written to this
825 In this example a pseudo-locked region named "newlock" was created. Here is
859 In this example a pseudo-locked region named "newlock" was created on the L2
872 # _-----=> irqs-off
873 # / _----=> need-resched
874 # | / _---=> hardirq/softirq
875 # || / _--=> preempt-depth
877 # TASK-PID CPU# |||| TIMESTAMP FUNCTION
879 pseudo_lock_mea-1672 [002] .... 3132.860500: pseudo_lock_l2: hits=4097 miss=0
888 for cache bit masks, minimum b/w of 10% with a memory bandwidth
892 # mount -t resctrl resctrl /sys/fs/resctrl
906 maximum memory b/w of 50% on socket0 and 50% on socket 1.
907 Tasks in group "p1" may also use 50% memory b/w on both sockets.
908 Note that unlike cache masks, memory b/w cannot specify whether these
914 max b/w in MB rather than the percentage values.
920 In the above example the tasks in "p1" and "p0" on socket 0 would use a max b/w
925 Again two sockets, but this time with a more realistic 20-bit mask.
928 processor 1 on socket 0 on a 2-socket and dual core machine. To avoid noisy
929 neighbors, each of the two real-time tasks exclusively occupies one quarter
933 # mount -t resctrl resctrl /sys/fs/resctrl
937 50% of the L3 cache on socket 0 and 50% of memory b/w cannot be used by
956 # taskset -cp 1 1234
963 # taskset -cp 2 5678
965 For the same 2 socket system with memory b/w resource and CAT L3 the
969 For our first real time task this would request 20% memory b/w on socket 0.
972 # echo -e "L3:0=f8000;1=fffff\nMB:0=20;1=100" > p0/schemata
974 For our second real time task this would request an other 20% memory b/w
978 # echo -e "L3:0=f8000;1=fffff\nMB:0=20;1=100" > p0/schemata
982 A single socket system which has real-time tasks running on core 4-7 and
983 non real-time workload assigned to core 0-3. The real-time tasks share text
989 # mount -t resctrl resctrl /sys/fs/resctrl
993 50% of the L3 cache on socket 0, and 50% of memory bandwidth on socket 0
999 to the "top" 50% of the cache on socket 0 and 50% of memory bandwidth on
1006 Finally we move core 4-7 over to the new group and make sure that the
1008 also get 50% of memory bandwidth assuming that the cores 4-7 are SMT
1009 siblings and only the real time threads are scheduled on the cores 4-7.
1022 system with two L2 cache instances that can be configured with an 8-bit
1027 # mount -t resctrl resctrl /sys/fs/resctrl/
1044 -sh: echo: write error: Invalid argument
1079 -sh: echo: write error: Invalid argument
1083 Example of Cache Pseudo-Locking
1085 Lock portion of L2 cache from cache id 1 using CBM 0x3. Pseudo-locked
1090 # mount -t resctrl resctrl /sys/fs/resctrl/
1093 Ensure that there are bits available that can be pseudo-locked, since only
1094 unused bits can be pseudo-locked the bits to be pseudo-locked needs to be
1103 Create a new resource group that will be associated with the pseudo-locked
1104 region, indicate that it will be used for a pseudo-locked region, and
1105 configure the requested pseudo-locked region capacity bitmask::
1108 # echo pseudo-locksetup > newlock/mode
1111 On success the resource group's mode will change to pseudo-locked, the
1112 bit_usage will reflect the pseudo-locked region, and the character device
1113 exposing the pseudo-locked region will exist::
1116 pseudo-locked
1119 # ls -l /dev/pseudo_lock/newlock
1120 crw------- 1 root root 243, 0 Apr 3 05:01 /dev/pseudo_lock/newlock
1125 * Example code to access one page of pseudo-locked cache region
1138 * cores associated with the pseudo-locked region. Here the cpu
1175 /* Application interacts with pseudo-locked memory @mapping */
1189 ----------------------------
1197 1. Read the cbmmasks from each directory or the per-resource "bit_usage"
1228 $ flock -s /sys/fs/resctrl/ find /sys/fs/resctrl
1232 $ cat create-dir.sh
1234 mask = function-of(output.txt)
1238 $ flock /sys/fs/resctrl/ ./create-dir.sh
1257 exit(-1);
1269 exit(-1);
1281 exit(-1);
1290 if (fd == -1) {
1292 exit(-1);
1306 ----------------------
1313 ------------------------------------------------------------------------
1317 # mount -t resctrl resctrl /sys/fs/resctrl
1357 --------------------------------------------
1360 # mount -t resctrl resctrl /sys/fs/resctrl
1377 ---------------------------------------------------------------------
1388 # mount -t resctrl resctrl /sys/fs/resctrl
1412 -----------------------------------
1414 A single socket system which has real time tasks running on cores 4-7
1419 # mount -t resctrl resctrl /sys/fs/resctrl
1423 Move the cpus 4-7 over to p1::
1435 Intel MBM Counters May Report System Memory Bandwidth Incorrectly
1436 -----------------------------------------------------------------
1440 Problem: Intel Memory Bandwidth Monitoring (MBM) counters track metrics
1443 metrics, may report incorrect system bandwidth for certain RMID values.
1445 Implication: Due to the errata, system memory bandwidth may not match
1451 +---------------+---------------+---------------+-----------------+
1453 +---------------+---------------+---------------+-----------------+
1455 +---------------+---------------+---------------+-----------------+
1457 +---------------+---------------+---------------+-----------------+
1459 +---------------+---------------+---------------+-----------------+
1461 +---------------+---------------+---------------+-----------------+
1463 +---------------+---------------+---------------+-----------------+
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1471 +---------------+---------------+---------------+-----------------+
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1515 …958/https://www.intel.com/content/www/us/en/processors/xeon/scalable/xeon-scalable-spec-update.html
1517 2. Erratum BDF102 in Intel Xeon E5-2600 v4 Processor Product Family Specification Update:
1518 …w.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-v4-spec-update.pdf
1521 …are.intel.com/content/www/us/en/develop/articles/intel-resource-director-technology-rdt-reference-…