Lines Matching full:bandwidth
25 MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
26 MBA (Memory Bandwidth Allocation) "mba"
27 SMBA (Slow Memory Bandwidth Allocation) ""
28 BMEC (Bandwidth Monitoring Event Configuration) ""
48 bandwidth in MiBps
138 Memory bandwidth(MB) subdirectory contains the following files
142 The minimum memory bandwidth percentage which
146 The granularity in which the memory bandwidth
150 available bandwidth control steps are:
161 request different memory bandwidth percentages:
167 bandwidth percentages are directly applied to
188 If the system supports Bandwidth Monitoring Event
189 Configuration (BMEC), then the bandwidth events will
201 and mbm_local_bytes events, respectively, when the Bandwidth
205 changed, the bandwidth counters for all RMIDs of both events
390 Reading this file shows which memory bandwidth event is used
391 as input to the software feedback loop that keeps memory bandwidth
393 name of one of the supported memory bandwidth events found in
515 Memory bandwidth allocation is still performed at the L3 cache
524 Memory bandwidth Allocation and monitoring
527 For Memory bandwidth resource, by default the user controls the resource
528 by indicating the percentage of total memory bandwidth.
530 The minimum bandwidth percentage value for each cpu model is predefined
531 and can be looked up through "info/MB/min_bandwidth". The bandwidth
533 be looked up at "info/MB/bandwidth_gran". The available bandwidth
537 The bandwidth throttling is a core specific mechanism on some of Intel
538 SKUs. Using a high bandwidth and a low bandwidth setting on two threads
540 low bandwidth (see "thread_throttle_mode").
542 The fact that Memory bandwidth allocation(MBA) may be a core
543 specific mechanism where as memory bandwidth monitoring(MBM) is done at
545 via the MBA and then monitor the bandwidth to see if the controls are
548 1. User may *not* see increase in actual bandwidth when percentage
551 This can occur when aggregate L2 external bandwidth is more than L3
552 external bandwidth. Consider an SKL SKU with 24 cores on a package and
553 where L2 external is 10GBps (hence aggregate L2 external bandwidth is
554 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
555 threads, having 50% bandwidth, each consuming 5GBps' consumes the max L3
556 bandwidth of 100GBps although the percentage value specified is only 50%
557 << 100%. Hence increasing the bandwidth percentage will not yield any
558 more bandwidth. This is because although the L2 external bandwidth still
559 has capacity, the L3 external bandwidth is fully used. Also note that
562 2. Same bandwidth percentage may mean different actual bandwidth
565 For the same SKU in #1, a 'single thread, with 10% bandwidth' and '4
566 thread, with 10% bandwidth' can consume upto 10GBps and 40GBps although
567 they have same percentage bandwidth of 10%. This is simply because as
568 threads start using more cores in an rdtgroup, the actual bandwidth may
569 increase or vary although user specified bandwidth percentage is same.
572 resctrl added support for specifying the bandwidth in MiBps as well. The
574 Controller(mba_sc)" which reads the actual bandwidth using MBM counters
575 and adjust the memory bandwidth percentages to ensure::
577 "actual bandwidth < user specified bandwidth".
579 By default, the schemata would take the bandwidth percentage values
611 Memory bandwidth Allocation (default mode)
619 Memory bandwidth Allocation specified in MiBps
622 Memory bandwidth domain is L3 cache.
627 Slow Memory Bandwidth Allocation (SMBA)
629 AMD hardware supports Slow Memory Bandwidth Allocation (SMBA).
631 support of SMBA, the hardware enables bandwidth allocation on
640 The bandwidth domain for slow memory is L3 cache. Its schemata file
663 Reading the schemata file will show the current bandwidth limit on all
666 configure the bandwidth limit.
888 for cache bit masks, minimum b/w of 10% with a memory bandwidth
993 50% of the L3 cache on socket 0, and 50% of memory bandwidth on socket 0
999 to the "top" 50% of the cache on socket 0 and 50% of memory bandwidth on
1008 also get 50% of memory bandwidth assuming that the cores 4-7 are SMT
1435 Intel MBM Counters May Report System Memory Bandwidth Incorrectly
1440 Problem: Intel Memory Bandwidth Monitoring (MBM) counters track metrics
1443 metrics, may report incorrect system bandwidth for certain RMID values.
1445 Implication: Due to the errata, system memory bandwidth may not match