Lines Matching +full:riscv +full:- +full:v +full:- +full:spec

1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
15 these interfaces is to give init systems a way to modify the availability of V
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
20 to use in a portable code. To get the availability of V in an ELF program,
27     argument consists of two 2-bit enablement statuses and a bit for inheritance
30     Enablement status is a tri-state value each occupying 2-bit of space in
33     * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
34       enablement status on execve(). The system-wide default setting can be
43     arg: The control argument is a 5-bit value consisting of 3 parts, and
64           then the enablement status will be decided by the system-wide
71           This setting persists across changes in the system-wide default value.
92     next execve() call and the inheritance bit are all OR-ed together.
94     Note that ELF programs are able to get the availability of V for itself by
103 -----------------------------------------
135 ---------------------------------------------
137 As indicated by version 1.0 of the V extension [1], vector registers are
140 1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc