Lines Matching full:accesses

250   the performance of misaligned scalar native word accesses on the selected set
254     misaligned scalar accesses is unknown.
257     accesses are emulated via software, either in or below the kernel.  These
258     accesses are always extremely slow.
261     word sized accesses are slower than the equivalent quantity of byte
262     accesses. Misaligned accesses may be supported directly in hardware, or
266     word sized accesses are faster than the equivalent quantity of byte
267     accesses.
270     accesses are not supported at all and will generate a misaligned address
282      performance of misaligned vector accesses on the selected set of processors.
285     vector accesses is unknown.
287   * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector
288     registers are slower than the equivalent quantity of byte accesses via vector registers.
289     Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.
291   * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector
292     registers are faster than the equivalent quantity of byte accesses via vector registers.
294   * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are