Lines Matching +full:non +full:- +full:active
49 transactional or non-transactional accesses within the system. In this
50 example, the transaction completes as though it were normal straight-line code
69 - Conflicts with cache lines used by other processors
70 - Signals
71 - Context switches
72 - See the ISA for full documentation of everything that will abort transactions.
78 Syscalls made from within an active transaction will not be performed and the
90 Care must be taken when relying on syscalls to abort during active transactions
109 determine the transactional state -- if so, the second ucontext in uc->uc_link
110 represents the active transactional registers at the point of the signal.
112 For 64-bit processes, uc->uc_mcontext.regs->msr is a full 64-bit MSR and its TS
115 For 32-bit processes, the mcontext's MSR register is only 32 bits; the top 32
117 uc->uc_link->uc_mcontext.regs->msr. The top word contains the transactional
123 Transaction-aware signal handlers can read the transactional register state
132 ucontext_t *transactional_ucp = ucp->uc_link;
135 u64 msr = ucp->uc_mcontext.regs->msr;
138 msr |= ((u64)transactional_ucp->uc_mcontext.regs->msr) << 32;
144 ucp->uc_mcontext.regs->nip,
145 transactional_ucp->uc_mcontext.regs->nip);
149 fix_the_problem(ucp->dar);
152 When in an active transaction that takes a signal, we need to be careful with
156 transactional memory state. If we write over this non transactionally or in
161 To avoid this, when taking a signal in an active transaction, we need to use
168 For signals taken in non-TM or suspended mode, we use the
169 normal/non-checkpointed stack pointer.
184 TM_CAUSE_SYSCALL Syscall from active transaction.
198 GDB and ptrace are not currently TM-aware. If one stops during a transaction,
253 -------------------
260 have SRR0 TM = 0 and TS = 00 (ie. TM off and non transaction) and the
263 be a transition from TS=01 to TS=00 (ie. suspend -> non transactional)
270 MSR 29:31 <- SRR1 29:31