Lines Matching full:accelerator

2 Coherent Accelerator Interface (CXL)
8     The coherent accelerator interface is designed to allow the
11     Accelerator Interface Architecture (CAIA).
13     IBM refers to this as the Coherent Accelerator Processor Interface
17     Coherent in this context means that the accelerator and CPUs can
47     The POWER Service Layer (PSL) and the Accelerator Function Unit
53     The AFU is the core part of the accelerator (eg. the compression,
87     this mode, only one userspace process can use the accelerator at
92     applications may use the accelerator (although specific AFUs may
103     A portion of the accelerator MMIO space can be directly mapped
404     FPGA accelerator. Once the image is written and verified, the