Lines Matching full:openrisc
2 OpenRISC Linux
5 This is a port of Linux to the OpenRISC class of microprocessors; the initial
6 target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
8 For information about OpenRISC processors and ongoing development:
11 website https://openrisc.io
12 email openrisc@lists.librecores.org
17 Build instructions for OpenRISC toolchain and Linux
20 In order to build and run Linux for OpenRISC, you'll need at least a basic
26 Toolchain binaries can be obtained from openrisc.io or our github releases page.
27 Instructions for building the different toolchains can be found on openrisc.io
31 binaries https://github.com/openrisc/or1k-gcc/releases
32 toolchains https://openrisc.io/software
40 make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig
41 make ARCH=openrisc CROSS_COMPILE="or1k-linux-"
45 The OpenRISC community typically uses FuseSoC to manage building and programming
47 development board with the OpenRISC SoC. During the build FPGA RTL is code
70 QEMU is a processor emulator which we recommend for simulating the OpenRISC
71 platform. Please follow the OpenRISC instructions on the QEMU website to get
73 likely provides binary packages to support OpenRISC.
76 qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC
88 openrisc: the OpenRISC class of processors
89 or1k: the OpenRISC 1000 family of processors
90 or1200: the OpenRISC 1200 processor
99 initial port of linux to OpenRISC/or32 architecture.