Lines Matching +full:inter +full:- +full:processor
1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
27 +-----+ +---------+ +-------+
28 | IPI | --> | CPUINTC | <-- | Timer |
29 +-----+ +---------+ +-------+
32 +---------+ +-------+
33 | LIOINTC | <-- | UARTs |
34 +---------+ +-------+
37 +-----------+
39 +-----------+
42 +---------+ +---------+
43 | PCH-PIC | | PCH-MSI |
44 +---------+ +---------+
47 +---------+ +---------+ +---------+
48 | PCH-LPC | | Devices | | Devices |
49 +---------+ +---------+ +---------+
52 +---------+
54 +---------+
59 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
64 +-----+ +---------+ +-------+
65 | IPI | --> | CPUINTC | <-- | Timer |
66 +-----+ +---------+ +-------+
69 +---------+ +---------+ +-------+
70 | EIOINTC | | LIOINTC | <-- | UARTs |
71 +---------+ +---------+ +-------+
74 +---------+ +---------+
75 | PCH-PIC | | PCH-MSI |
76 +---------+ +---------+
79 +---------+ +---------+ +---------+
80 | PCH-LPC | | Devices | | Devices |
81 +---------+ +---------+ +---------+
84 +---------+
86 +---------+
91 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt
92 go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
93 devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
96 +-----+ +-------------------+ +-------+
97 | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
98 +-----+ +-------------------+ +-------+
101 +-----------+
102 | V-EIOINTC |
103 +-----------+
106 +---------+ +---------+
107 | PCH-PIC | | PCH-MSI |
108 +---------+ +---------+
111 +--------+ +---------+ +---------+
113 +--------+ +---------+ +---------+
117 -----------
118 V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
120 be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
127 CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in
130 With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
131 there are two newly added registers with V-EIOINTC.
134 --------------------
135 This register is read-only register, which indicates supported features with
136 V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.
140 bitmap method, so interrupt can be routed to IP0 - IP15.
142 Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
144 so interrupt can be routed to CPU0 - CPU255.
147 ------------------
148 This register is read-write register, for compatibility intterupt routed uses
155 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
156 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
158 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
160 +-----+ +-----------------------+ +-------+
161 | IPI | --> | CPUINTC | <-- | Timer |
162 +-----+ +-----------------------+ +-------+
165 +---------+ +----------+ +---------+ +-------+
166 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
167 +---------+ +----------+ +---------+ +-------+
170 +---------+ +---------+
171 | PCH-PIC | | PCH-MSI |
172 +---------+ +---------+
175 +---------+ +---------+ +---------+
176 | Devices | | PCH-LPC | | Devices |
177 +---------+ +---------+ +---------+
180 +---------+
182 +---------+
184 ACPI-related definitions
211 PCH-PIC::
217 PCH-MSI::
223 PCH-LPC::
232 Documentation of Loongson-3A5000:
234 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-userm…
236 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-userm…
240 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-userm…
242 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-userm…
245 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
247 - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
248 "Loongson 3A5000 Processor Reference Manual";
249 - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
250 "Loongson 3A5000 Processor Reference Manual";
251 - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
252 "Loongson 3A5000 Processor Reference Manual";
253 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
255 - PCH-LPC is "LPC Interrupts" described in Section 24.3 of