Lines Matching full:eiointc

9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
70                 | EIOINTC | | LIOINTC | <-- | UARTs |
93 devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
102                       | V-EIOINTC |
118 V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
119 EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
120 be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
123 With standard EIOINTC, interrupt routing setting includes two parts: eight
125 For CPU selection there is four bits for EIOINTC node selection, four bits
126 for EIOINTC CPU selection. Bitmap method is used for CPU selection and
128 one EIOINTC node.
130 With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
131 there are two newly added registers with V-EIOINTC.
136 V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.
138 Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
142 Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
149 the default method which is the same with standard EIOINTC. If the bit is set
158 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
166        | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
199 EIOINTC::
249     - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of