Lines Matching +full:2 +full:w
81 There are currently 2 vector extensions to LoongArch:
129 0x22 Privileged Resource Configuration 2 PRCFG2
139 0x81 Implementation-specific Control 2 IMPCTL2
157 0x92 Machine Error Information 2 MERRINFO2
166 0x200+2n (0≤n≤31) Performance Monitor Configuration n PMCFGn
167 0x201+2n (0≤n≤31) Performance Monitor Overall Counter n PMCNTn
175 Configuration 2
187 Configuration 2
212 2R Opcode + Rj + Rd
215 2RI8 Opcode + I8 + Rj + Rd
216 2RI12 Opcode + I12 + Rj + Rd
217 2RI14 Opcode + I14 + Rj + Rd
218 2RI16 Opcode + I16 + Rj + Rd
238 ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
241 MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
244 LU12I.W LU32I.D LU52I.D ADDU16I.D
246 2. Bit-shift Instructions::
248 SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
253 EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
254 BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
255 REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
264 LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
265 LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
266 LDPTR.W LDPTR.D STPTR.W STPTR.D
271 LL.W SC.W LL.D SC.D
272 AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
273 AMMAX.W AMMAX.D AMMIN.W AMMIN.D
281 SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D
287 IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
338 for coherent cached, and 2 is for weakly-ordered uncached.
353 the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series,