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14 model. To aid understanding, a minimal description of relevant programmer's
15 model features for SME is included in Appendix A.
19 -----------
21 * PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
26 instructions and registers, and the Linux-specific system interfaces
31 the SME2 instructions and ZT0, and the Linux-specific system interfaces
42 * There are a number of optional SME features, presence of these is reported
58 cpu-feature-registers.txt for details.
62 way of detecting support for these regsets is to connect to a target process
63 first and then attempt a
67 * Whenever ZA register values are exchanged in memory between userspace and
68 the kernel, the register value is encoded in memory as a series of horizontal
69 vectors from 0 to VL/8-1 stored in the same endianness invariant format as is
76 ------------------
78 SME defines a second vector length similar to the SVE vector length which
79 controls the size of the streaming mode SVE vectors and the ZA matrix array.
80 The ZA matrix is square with each side having as many bytes as a streaming
84 3. Sharing of streaming and non-streaming mode SVE state
85 ---------------------------------------------------------
88 between streaming and non-streaming modes. When switching between modes
95 -------------------------
97 * On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the
98 ZA matrix and ZTn (if present) are preserved.
103 * None of the SVE registers, ZA or ZTn are used to pass arguments to
109 * All other SME state of a thread, including the currently configured vector
116 -------------------
118 * Signal handlers are invoked with streaming mode and ZA disabled.
120 * A new signal frame record TPIDR2_MAGIC is added formatted as a struct
123 * A new signal frame record za_context encodes the ZA register contents on
126 * The signal frame record for ZA always contains basic metadata, in particular
129 * The ZA matrix may or may not be included in the record, depending on
130 the value of PSTATE.ZA. The registers are present if and only if:
132 in which case PSTATE.ZA == 1.
134 * If matrix data is present, the remainder of the record has a vl-dependent
138 * The matrix is stored as a series of horizontal vectors in the same format as
141 * If the ZA context is too big to fit in sigcontext.__reserved[], then extra
146 * If ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will
149 * The signal record for ZTn has magic ZT_MAGIC (0x5a544e01) and consists of a
150 standard signal frame header followed by a struct zt_context specifying
156 -----------------
158 When returning from a signal handler:
162 then ZA is disabled.
165 PSTATE.ZA is set to 1 and ZA is populated with the specified data.
169 attempt is treated as illegal, resulting in a forced SIGSEGV.
171 * If ZTn is not supported or PSTATE.ZA==0 then it is illegal to have a
172 signal frame record for ZTn, resulting in a forced SIGSEGV.
176 --------------------
194 Section 9.)
206 This allows launching of a new program with a different vector
213 Return value: a nonnegative on success, or a negative value on error:
237 * Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all
238 bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
239 unspecified, including both streaming and non-streaming SVE state.
242 does not constitute a change to the vector length for this purpose.
244 * Changing the vector length causes PSTATE.ZA and PSTATE.SM to be cleared.
247 does not constitute a change to the vector length for this purpose.
254 The following flag may be OR-ed into the result:
261 vector length change (which would only normally be the case between a
267 Return value: a nonnegative value on success, or a negative value on error:
272 ---------------------
274 * A new regset NT_ARM_SSVE is defined for access to streaming mode SVE
278 * A new regset NT_ARM_ZA is defined for ZA state for access to ZA state via
290 If a call to PTRACE_GETREGSET requests less data than the value of
291 size, the caller can allocate a larger buffer and retry in order to
320 The caller must make a further GETREGSET call if it needs to know what VL is
328 case the vector length and flags are changed and PSTATE.ZA is set to 0
329 (along with any consequences of those changes). If a payload is provided
330 then PSTATE.ZA will be set to 1.
338 * The effect of writing a partial, incomplete payload is unspecified.
340 * A new regset NT_ARM_ZT is defined for access to ZTn state via
343 * The NT_ARM_ZT regset consists of a single 512 bit register.
345 * When PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZTn as 0.
347 * Writes to NT_ARM_ZT will set PSTATE.ZA to 1.
355 ---------------------------
359 data that would have been read if a PTRACE_GETREGSET of the corresponding
362 * A NT_ARM_ZA note will be added to each coredump for each thread of the
364 been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread
367 * A NT_ARM_ZT note will be added to each coredump for each thread of the
369 been read if a PTRACE_GETREGSET of NT_ARM_ZT were executed for each thread
376 9. System runtime configuration
377 --------------------------------
379 * To mitigate the ABI impact of expansion of the signal frame, a policy
386 default vector length to the specified value rounded to a supported value
404 * a deferred vector length change is pending, established via the
411 Appendix A. SME programmer's model (informative)
414 This section provides a minimal description of the additions made by SME to the
415 ARMv8-A programmer's model that are relevant to this document.
420 A.1. Registers
421 ---------------
425 * A new mode, streaming mode, in which a subset of the normal FPSIMD and SVE
432 * A new vector length controlling the size of ZA and the Z registers when in
436 a given system have any relationship. The streaming mode vector length
439 * A new ZA matrix register. This is a square matrix of SVLxSVL bits. Most
440 operations on ZA require that streaming mode be enabled but ZA can be
444 ZA only when it is actively being used.
446 * A new ZT0 register is introduced when SME2 is present. This is a 512 bit
447 register which is accessible when PSTATE.ZA is set, as ZA itself is.
452 * PSTATE.ZA, if this is 1 then the ZA matrix is accessible and has valid
453 data while if it is 0 then ZA can not be accessed. When PSTATE.ZA is
454 changed from 0 to 1 all bits in ZA are cleared.
471 [3] Documentation/arch/arm64/cpu-feature-registers.rst