Lines Matching full:initialised
210 level where the kernel image will be entered must be initialised by
224 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
229 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
230 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
237 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
238 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
247 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
251 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
259 - SCR_EL3.APK (bit 16) must be initialised to 0b1
260 - SCR_EL3.API (bit 17) must be initialised to 0b1
264 - HCR_EL2.APK (bit 40) must be initialised to 0b1
265 - HCR_EL2.API (bit 41) must be initialised to 0b1
271 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
272 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
273 - AMCNTENSET0_EL0 must be initialised to 0b1111
274 - AMCNTENSET1_EL0 must be initialised to a platform specific value
280 - AMCNTENSET0_EL0 must be initialised to 0b1111
281 - AMCNTENSET1_EL0 must be initialised to a platform specific value
289 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
295 - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
301 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
307 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
311 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
317 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
319 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
324 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
326 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
328 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
335 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
337 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
339 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
344 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
346 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
348 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
350 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
353 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
355 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
357 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
359 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
365 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
369 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
375 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
379 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
385 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
389 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
395 - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.
399 - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
400 - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
401 - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
403 - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
404 - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
405 - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
411 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
413 - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1 and the hypervisor
420 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
424 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
430 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
434 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
436 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
438 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
440 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
444 - GCSCR_EL1 must be initialised to 0.
446 - GCSCRE0_EL1 must be initialised to 0.
450 - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1.
454 - GCSCR_EL2 must be initialised to 0.
458 - HCRX_EL2.GCSEn must be initialised to 0b1.
460 - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1.
462 - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1.
464 - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1.
466 - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
468 - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
470 - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
472 - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.