Lines Matching +full:fiq +full:- +full:based
9 This document is based on the ARM booting document by Russell King and
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
33 ---------------------------
49 -------------------------
53 The device tree blob (dtb) must be placed on an 8-byte boundary and must
62 ------------------------------
74 ------------------------
78 The decompressed kernel image contains a 64-byte header as follows::
94 - As of v3.17, all fields are little endian unless stated otherwise.
96 - code0/code1 are responsible for branching to stext.
98 - when booting through EFI, code0/code1 are initially skipped.
103 - Prior to v3.17, the endianness of text_offset was not specified. In
105 endianness of the kernel. Where image_size is non-zero image_size is
106 little-endian and must be respected. Where image_size is zero,
109 - The flags field (introduced in v3.17) is a little-endian 64-bit field
114 Bit 1-2 Kernel Page size.
116 * 0 - Unspecified.
117 * 1 - 4K
118 * 2 - 16K
119 * 3 - 64K
129 the 48-bit addressable range of physical memory
130 Bits 4-63 Reserved.
133 - When image_size is zero, a bootloader should attempt to keep as much
159 - Quiesce all DMA capable devices so that memory does not get
163 - Primary CPU general-purpose register settings:
165 - x0 = physical address of device tree blob (dtb) in system RAM.
166 - x1 = 0 (reserved for future use)
167 - x2 = 0 (reserved for future use)
168 - x3 = 0 (reserved for future use)
170 - CPU mode
173 IRQ and FIQ).
174 The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
177 - Caches, MMUs
193 - Architected timers
200 - Coherency
207 - System registers
215 - If EL3 is present:
217 - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
219 - The value of SCR_EL3.FIQ must be the same as the one present at boot
222 - If EL3 is present and the kernel is entered at EL2:
224 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
227 - If EL3 is present:
229 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
230 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
231 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
235 - If the kernel is entered at EL1:
237 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
238 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
240 - The DT or ACPI tables must describe a GICv3 interrupt controller.
245 - If EL3 is present:
249 - If the kernel is entered at EL1:
253 - The DT or ACPI tables must describe a GICv2 interrupt controller.
257 - If EL3 is present:
259 - SCR_EL3.APK (bit 16) must be initialised to 0b1
260 - SCR_EL3.API (bit 17) must be initialised to 0b1
262 - If the kernel is entered at EL1:
264 - HCR_EL2.APK (bit 40) must be initialised to 0b1
265 - HCR_EL2.API (bit 41) must be initialised to 0b1
269 - If EL3 is present:
271 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
272 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
273 - AMCNTENSET0_EL0 must be initialised to 0b1111
274 - AMCNTENSET1_EL0 must be initialised to a platform specific value
278 - If the kernel is entered at EL1:
280 - AMCNTENSET0_EL0 must be initialised to 0b1111
281 - AMCNTENSET1_EL0 must be initialised to a platform specific value
287 - If EL3 is present and the kernel is entered at EL2:
289 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
293 - If EL3 is present and the kernel is entered at EL2:
295 - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
299 - If EL3 is present and the kernel is entered at EL2:
301 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
305 - If EL3 is present:
307 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
309 - If EL2 is present and the kernel is entered at EL1:
311 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
315 - if EL3 is present:
317 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
319 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
322 - If the kernel is entered at EL1 and EL2 is present:
324 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
326 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
328 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
333 - If EL3 is present:
335 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
337 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
339 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
342 - If the kernel is entered at EL1 and EL2 is present:
344 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
346 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
348 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
350 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
353 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
355 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
357 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
359 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
363 - If EL3 is present:
365 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
367 - If the kernel is entered at EL1 and EL2 is present:
369 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
373 - If EL3 is present:
375 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
377 - If the kernel is entered at EL1 and EL2 is present:
379 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
383 - If EL3 is present:
385 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
387 - If the kernel is entered at EL1 and EL2 is present:
389 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
393 - If EL3 is present:
395 - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.
397 - If the kernel is entered at EL1 and EL2 is present:
399 - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
400 - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
401 - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
403 - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
404 - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
405 - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
409 - If the kernel is entered at EL1 and EL2 is present:
411 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
413 - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1 and the hypervisor
418 - If EL3 is present:
420 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
422 - If the kernel is entered at EL1 and EL2 is present:
424 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
428 - If EL3 is present:
430 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
432 - If the kernel is entered at EL1 and EL2 is present:
434 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
436 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
438 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
440 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
442 - For CPUs with Guarded Control Stacks (FEAT_GCS):
444 - GCSCR_EL1 must be initialised to 0.
446 - GCSCRE0_EL1 must be initialised to 0.
448 - If EL3 is present:
450 - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1.
452 - If EL2 is present:
454 - GCSCR_EL2 must be initialised to 0.
456 - If the kernel is entered at EL1 and EL2 is present:
458 - HCRX_EL2.GCSEn must be initialised to 0b1.
460 - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1.
462 - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1.
464 - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1.
466 - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
468 - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
470 - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
472 - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
474 - For CPUs with debug architecture i.e FEAT_Debugv8pN (all versions):
476 - If EL3 is present:
478 - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
480 - For CPUs with FEAT_PMUv3:
482 - If EL3 is present:
484 - MDCR_EL3.TPM (bit 6) must be initialized to 0b0
496 - The primary CPU must jump directly to the first instruction of the
498 an 'enable-method' property for each cpu node. The supported
499 enable-methods are described below.
504 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
506 naturally-aligned 64-bit zero-initalised memory location.
510 device tree) polling their cpu-release-addr location, which must be
512 to reduce the overhead of the busy-loop and a sev will be issued by
514 cpu-release-addr returns a non-zero value, the CPU must jump to this
515 value. The value will be written as a single 64-bit little-endian
519 - CPUs with a "psci" enable method should remain outside of
530 - Secondary CPU general-purpose register settings
532 - x0 = 0 (reserved for future use)
533 - x1 = 0 (reserved for future use)
534 - x2 = 0 (reserved for future use)
535 - x3 = 0 (reserved for future use)