Lines Matching full:cpus

196   be programmed with a consistent value on all CPUs.  If entering the
202   All CPUs to be booted by the kernel must be part of the same coherency
217     - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
232         all CPUs the kernel is executing on, and must stay constant
255   For CPUs with pointer authentication functionality:
267   For CPUs with Activity Monitors Unit v1 (AMUv1) extension present:
285   For CPUs with the Fine Grained Traps (FEAT_FGT) extension present:
291   For CPUs with the Fine Grained Traps 2 (FEAT_FGT2) extension present:
297   For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
303   For CPUs with Advanced SIMD and floating point support:
313   For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
319     - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
328     - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
331   For CPUs with the Scalable Matrix Extension (FEAT_SME):
339     - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
350     - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
361   For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64):
371   For CPUs with the Memory Tagging Extension feature (FEAT_MTE2):
381   For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2):
391   For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9):
407   For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):
416   For CPUs with the Extended Translation Control Register feature (FEAT_TCR2):
426   For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE):
442  - For CPUs with Guarded Control Stacks (FEAT_GCS):
474  - For CPUs with debug architecture i.e FEAT_Debugv8pN (all versions):
480  - For CPUs with FEAT_PMUv3:
487 timers, coherency and system registers apply to all CPUs.  All CPUs must
504 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
508   These CPUs should spin outside of the kernel in a reserved area of
516   value, so CPUs must convert the read value to their native endianness
519 - CPUs with a "psci" enable method should remain outside of
525   processors") to bring CPUs into the kernel.