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4 STM32 DMA-MDMA chaining
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
14 To offload data transfers from the CPU, STM32 microprocessors (MPUs) embed
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
19 (STM32 DMAMUX).
21 **STM32 DMAMUX**
23 STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA
24 controller (STM32MP1 counts two STM32 DMA controllers) channels.
26 **STM32 DMA**
28 STM32 DMA is mainly used to implement central data buffer storage (usually in
33 **STM32 MDMA**
35 STM32 MDMA (Master DMA) is mainly used to manage direct data transfers between
37 hierarchical structure that uses STM32 DMA as first level data buffer
38 interfaces for AHB peripherals, while the STM32 MDMA acts as a second level
39 DMA with better performance. As a AXI/AHB master, STM32 MDMA can take control
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
47 STM32 MDMA controllers.
49 STM32 DMA has a circular Double Buffer Mode (DBM). At each end of transaction
52 counter is automatically reloaded. This allows the SW or the STM32 MDMA to
54 the STM32 DMA transfer.
56 With STM32 MDMA linked-list mode, a single request initiates the data array
62 STM32 MDMA has direct connections with STM32 DMA. This enables autonomous
64 resources and bus congestion. Transfer Complete signal of STM32 DMA channel
65 can triggers STM32 MDMA transfer. STM32 MDMA can clear the request generated
66 by the STM32 DMA by writing to its Interrupt Clear register (whose address is
69 .. table:: STM32 MDMA interconnect table with STM32 DMA
72 | STM32 DMAMUX | STM32 DMA | STM32 DMA | STM32 MDMA |
110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
112 Due to STM32 DMA legacy (within microcontrollers), STM32 DMA performances are
114 between STM32 DMA and STM32 MDMA. This buffer is split in two equal periods
115 and STM32 DMA uses one period while STM32 MDMA uses the other period
122 | STM32 DMA | / __|>_ \ | STM32 MDMA |
128 STM32 DMA-MDMA chaining uses (struct dma_slave_config).peripheral_config to
132 * the STM32 MDMA request (which is actually the DMAMUX channel ID),
133 * the address of the STM32 DMA register to clear the Transfer Complete
135 * the mask of the Transfer Complete interrupt flag of the STM32 DMA channel.
137 Device Tree updates for STM32 DMA-MDMA chaining support
154 STM32 DMA and STM32 MDMA can work simultaneously, on each buffer of the
156 If the SRAM period is greater than the expected DMA transfer, then STM32 DMA
157 and STM32 MDMA will work sequentially instead of simultaneously. It is not a
171 **2. Allocate a STM32 DMA channel and a STM32 MDMA channel**
176 This new channel must be taken from STM32 MDMA channels, so, the phandle of
183 dmas = <&dmamux1 ...>, // STM32 DMA channel
184 <&mdma1 0 0x3 0x1200000a 0 0>; // + STM32 MDMA channel
187 Concerning STM32 MDMA bindings:
190 by MDMA driver with the STM32 DMAMUX channel ID passed through
210 Driver updates for STM32 DMA-MDMA chaining support in foo driver
217 STM32 DMA transfer (where memory address targets now the SRAM buffer instead
218 of DDR buffer) and one for STM32 MDMA transfer (where memory address targets
245 /* Create sg table for STM32 DMA channel */
263 /* Create sg table for STM32 MDMA channel */
293 configure STM32 DMA channel. You just have to take care of DMA addresses,
297 STM32 DMA driver will check (struct dma_slave_config).peripheral_size to
298 determine if chaining is being used or not. If it is used, then STM32 DMA
300 three u32 : the first one containing STM32 DMAMUX channel ID, the second one
305 configure STM32 MDMA channel. Take care of DMA addresses, the device address
309 and .peripheral_config that have been updated by STM32 DMA driver, to set
311 struct dma_slave_config to configure STM32 MDMA channel.
334 **2. Get a descriptor for STM32 DMA channel transaction**
342 **3. Get a descriptor for STM32 MDMA channel transaction**
344 If you previously get descriptor (for STM32 DMA) with
347 STM32 MDMA;
349 STM32 MDMA.
371 As STM32 MDMA channel transfer is triggered by STM32 DMA, you must issue
372 STM32 MDMA channel before STM32 DMA channel.
377 Don't forget to terminate both channels. STM32 DMA channel is configured in
379 it. STM32 MDMA channel will be stopped by HW in case of sg transfer, but not
382 **STM32 DMA-MDMA chaining DMA_MEM_TO_DEV special case**
384 STM32 DMA-MDMA chaining in DMA_MEM_TO_DEV is a special case. Indeed, the
385 STM32 MDMA feeds the SRAM buffer with the DDR data, and the STM32 DMA reads
387 SRAM buffer when the STM32 DMA starts to read.
389 A trick could be pausing the STM32 DMA channel (that will raise a Transfer
390 Complete signal, triggering the STM32 MDMA channel), but the first data read
391 by the STM32 DMA could be "wrong". The proper way is to prepare the first SRAM
395 Due to this complexity, rather use the STM32 DMA-MDMA chaining for
406 dealing with STM32 DMAMUX, STM32 DMA and STM32 MDMA.
409 .. _AN5224: https://www.st.com/resource/en/application_note/an5224-stm32-dmamux-the-dma-request-rou…