Lines Matching full:traffic

31 The SCF PMU monitors system level cache events, CPU traffic, and
32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
34 traffic coverage.
52 The NVLink-C2C0 PMU monitors incoming traffic from a GPU/CPU connected with
53 NVLink-C2C (Chip-2-Chip) interconnect. The type of traffic captured by this PMU
58   In this config, the PMU captures GPU ATS translated or EGM traffic from the GPU.
66 the PMU traffic coverage.
108 The NVLink-C2C1 PMU monitors incoming traffic from a GPU connected with
110 traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic.
112 the PMU traffic coverage.
154 The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
155 to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
156 (RO) write traffic. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`
157 for more info about the PMU traffic coverage.
170 The PMU can not distinguish the remote traffic initiator, therefore it does not
171 provide filter to select the traffic source to monitor. It reports combined
172 traffic from remote GPU and PCIE devices.
176 * Count event id 0x0 for the traffic from remote socket 1, 2, and 3 to socket 0::
180 * Count event id 0x0 for the traffic from remote socket 0, 2, and 3 to socket 1::
184 * Count event id 0x0 for the traffic from remote socket 0, 1, and 3 to socket 2::
188 * Count event id 0x0 for the traffic from remote socket 0, 1, and 2 to socket 3::
196 The PCIE PMU monitors all read/write traffic from PCIE root ports to
198 for more info about the PMU traffic coverage.
222 Traffic Coverage
225 The PMU traffic coverage may vary dependent on the chip configuration:
256   | Following table contains traffic coverage of Grace SoC PMU in socket-A:
281    PCIE1 traffic represents strongly ordered (SO) writes.
282    PCIE2 traffic represents reads and relaxed ordered (RO) writes.
313   | Following table contains traffic coverage of Grace SoC PMU in socket-A:
332    PCIE1 traffic represents strongly ordered (SO) writes.
333    PCIE2 traffic represents reads and relaxed ordered (RO) writes.