Lines Matching +full:cpu +full:- +full:pcie
9 * NVLink-C2C0
10 * NVLink-C2C1
12 * PCIE
15 ----------
19 PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
22 the driver provides "cpumask" sysfs attribute to show the CPU id used to handle
29 -------
31 The SCF PMU monitors system level cache events, CPU traffic, and
32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
37 see /sys/bus/event_source/devices/nvidia_scf_pmu_<socket-id>.
43 perf stat -a -e nvidia_scf_pmu_0/event=0x0/
47 perf stat -a -e nvidia_scf_pmu_1/event=0x0/
49 NVLink-C2C0 PMU
50 --------------------
52 The NVLink-C2C0 PMU monitors incoming traffic from a GPU/CPU connected with
53 NVLink-C2C (Chip-2-Chip) interconnect. The type of traffic captured by this PMU
60 * NVIDIA Grace CPU Superchip: two Grace CPU SoCs are connected.
63 PCIE device of the remote SoC.
69 see /sys/bus/event_source/devices/nvidia_nvlink_c2c0_pmu_<socket-id>.
73 * Count event id 0x0 from the GPU/CPU connected with socket 0::
75 perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/
77 * Count event id 0x0 from the GPU/CPU connected with socket 1::
79 perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/
81 * Count event id 0x0 from the GPU/CPU connected with socket 2::
83 perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/
85 * Count event id 0x0 from the GPU/CPU connected with socket 3::
87 perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/
89 The NVLink-C2C has two ports that can be connected to one GPU (occupying both
99 perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/
103 perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/
105 NVLink-C2C1 PMU
106 -------------------
108 The NVLink-C2C1 PMU monitors incoming traffic from a GPU connected with
109 NVLink-C2C (Chip-2-Chip) interconnect. This PMU captures untranslated GPU
110 traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic.
115 see /sys/bus/event_source/devices/nvidia_nvlink_c2c1_pmu_<socket-id>.
121 perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0/
125 perf stat -a -e nvidia_nvlink_c2c1_pmu_1/event=0x0/
129 perf stat -a -e nvidia_nvlink_c2c1_pmu_2/event=0x0/
133 perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/
135 The NVLink-C2C has two ports that can be connected to one GPU (occupying both
145 perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/
149 perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/
152 ---------------
154 The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
155 to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
160 see /sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>.
167 /sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket
172 traffic from remote GPU and PCIE devices.
178 perf stat -a -e nvidia_cnvlink_pmu_0/event=0x0,rem_socket=0xE/
182 perf stat -a -e nvidia_cnvlink_pmu_1/event=0x0,rem_socket=0xD/
186 perf stat -a -e nvidia_cnvlink_pmu_2/event=0x0,rem_socket=0xB/
190 perf stat -a -e nvidia_cnvlink_pmu_3/event=0x0,rem_socket=0x7/
193 PCIE PMU
194 ------------
196 The PCIE PMU monitors all read/write traffic from PCIE root ports to
201 see /sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>.
207 /sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>/format/root_port
214 perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/
218 perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/
223 ----------------
232 * SOCKET-A * * SOCKET-B *
235 * : PCIE : * * : PCIE : *
241 * : GPU :<--NVLink-->: Grace :<---CNVLink--->: Grace :<--NVLink-->: GPU : *
253 CMEM = CPU Memory (e.g. LPDDR5X)
256 | Following table contains traffic coverage of Grace SoC PMU in socket-A:
260 +--------------+-------+-----------+-----------+-----+----------+----------+
262 + +-------+-----------+-----------+-----+----------+----------+
263 | Destination | |GPU ATS |GPU Not-ATS| | Socket-B | Socket-B |
264 | |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
267 | Local | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU | CNVLink |
269 +--------------+-------+-----------+-----------+-----+----------+----------+
270 | Local GMEM | PCIE | N/A |NVLink-C2C1| SCF | SCF PMU | CNVLink |
272 +--------------+-------+-----------+-----------+-----+----------+----------+
273 | Remote | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | | |
276 +--------------+-------+-----------+-----------+-----+----------+----------+
277 | Remote GMEM | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | | |
279 +--------------+-------+-----------+-----------+-----+----------+----------+
284 * **NVIDIA Grace CPU Superchip**: two Grace CPU SoCs are connected.
289 * SOCKET-A * * SOCKET-B *
292 * : PCIE : * * : PCIE : *
298 * : Grace :<--------NVLink------->: Grace : *
310 CMEM = CPU Memory (e.g. LPDDR5X)
313 | Following table contains traffic coverage of Grace SoC PMU in socket-A:
317 +-----------------+-----------+---------+----------+-------------+
319 + +-----------+---------+----------+-------------+
320 | Destination | | | Socket-B | Socket-B |
321 | | PCI R/W | CPU | CPU/PCIE1| PCIE2 |
324 | Local | PCIE PMU | SCF PMU | SCF PMU | NVLink-C2C0 |
326 +-----------------+-----------+---------+----------+-------------+
328 | SYSRAM/CMEM | PCIE PMU | SCF PMU | N/A | N/A |
329 | over NVLink-C2C | | | | |
330 +-----------------+-----------+---------+----------+-------------+