Lines Matching +full:interrupt +full:- +full:partition +full:-

1 .. SPDX-License-Identifier: GPL-2.0-only
15 AMD NPU (Neural Processing Unit) is a multi-user AI inference accelerator
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34 partition which can be bound to a workload context.
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55 XDNA Array partition setup, XDNA Array configuration, workload context
58 NPU Firmware uses a dedicated instance of an isolated non-privileged context
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82 MSI-X interrupt vectors. NPU uses a dedicated high bandwidth SoC level fabric
84 dedicated MSI-X interrupt. MERT gets a single instance of MSI-X interrupt.
96 On specific devices, the above-mentioned BAR type might be combined into a
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110 partition is setup by programming the column isolation registers by the
111 microcontroller. Each spatial partition is associated with a PASID which is
124 torn down dynamically to accommodate various workloads. A *spatial* partition
125 may be *exclusively* bound to one workload context while another partition may
127 updates the PASID for a temporarily shared partition to match the context that
128 has been bound to the partition at any moment.
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137 decide 2D array (re)partition strategy and mapping of workloads for spatial and
138 temporal sharing of columns. The FW enforces the context-to-column(s) resource
151 1. AMD XDNA Array overlay, which is used to configure a NPU spatial partition.
154    spatial partition bound to the workload by the associated ERT instance.
156    `Versal Adaptive SoC AIE-ML Architecture Manual (AM020)`_ for more details.
159    partition. ``ctrlcode`` is executed by the ERT running in protected mode on
168 Per-context Instruction Buffer
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185 High-level Use Flow
206 11. When ERT reaches end of ``ctrlcode``, it raises an MSI-X to send completion
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226 Peano is an LLVM based open-source compiler for AMD XDNA Array compute tile
228 https://github.com/Xilinx/llvm-aie
230 The open-source IREE compiler supports graph compilation of ML models for AMD
232 https://github.com/nod-ai/iree-amd-aie
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237 The open-source XRT runtime stack interfaces with amdxdna kernel driver. XRT
241 The open-source XRT shim for NPU is can be found at:
242 https://github.com/amd/xdna-driver
259 the register states for the partition bound to faulting workload context. The
268 * L1 interrupt counter
277 - `AMD XDNA Architecture <https://www.amd.com/en/technologies/xdna.html>`_
278 - `AMD AI Engine Technology <https://www.xilinx.com/products/technology/ai-engine.html>`_
279 - `Peano <https://github.com/Xilinx/llvm-aie>`_
280 - `Versal Adaptive SoC AIE-ML Architecture Manual (AM020) <https://docs.amd.com/r/en-US/am020-versa…
281 - `AI Engine Run Time <https://github.com/Xilinx/aie-rt/tree/release/main_aig>`_