Lines Matching +full:- +full:ge
28 // -----------------------------------------------------------------------------
30 // test/aarch32/config/template-assembler-aarch32.cc.in template file using
34 // -----------------------------------------------------------------------------
37 #include "test-runner.h"
39 #include "test-utils.h"
40 #include "test-utils-aarch32.h"
42 #include "aarch32/assembler-aarch32.h"
43 #include "aarch32/macro-assembler-aarch32.h"
96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
118 {{ge, r4, r4, ASR, r1}, true, ge, "ge r4 r4 ASR r1", "ge_r4_r4_ASR_r1"},
122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r3", "ge_r6_r6_ROR_r3"},
127 {{ge, r4, r4, LSL, r0}, true, ge, "ge r4 r4 LSL r0", "ge_r4_r4_LSL_r0"},
132 {{ge, r1, r1, ASR, r7}, true, ge, "ge r1 r1 ASR r7", "ge_r1_r1_ASR_r7"},
156 {{ge, r3, r3, ROR, r7}, true, ge, "ge r3 r3 ROR r7", "ge_r3_r3_ROR_r7"},
162 {{ge, r4, r4, ROR, r1}, true, ge, "ge r4 r4 ROR r1", "ge_r4_r4_ROR_r1"},
165 {{ge, r3, r3, LSL, r4}, true, ge, "ge r3 r3 LSL r4", "ge_r3_r3_LSL_r4"},
170 {{ge, r1, r1, ASR, r2}, true, ge, "ge r1 r1 ASR r2", "ge_r1_r1_ASR_r2"},
171 {{ge, r7, r7, LSR, r4}, true, ge, "ge r7 r7 LSR r4", "ge_r7_r7_LSR_r4"},
184 {{ge, r0, r0, LSR, r0}, true, ge, "ge r0 r0 LSR r0", "ge_r0_r0_LSR_r0"},
209 {{ge, r0, r0, LSR, r7}, true, ge, "ge r0 r0 LSR r7", "ge_r0_r0_LSR_r7"},
211 {{ge, r1, r1, LSL, r3}, true, ge, "ge r1 r1 LSL r3", "ge_r1_r1_LSL_r3"},
222 {{ge, r6, r6, LSL, r6}, true, ge, "ge r6 r6 LSL r6", "ge_r6_r6_LSL_r6"},
267 {{ge, r6, r6, ROR, r2}, true, ge, "ge r6 r6 ROR r2", "ge_r6_r6_ROR_r2"},
273 {{ge, r2, r2, LSR, r0}, true, ge, "ge r2 r2 LSR r0", "ge_r2_r2_LSR_r0"},
291 {{ge, r3, r3, LSL, r2}, true, ge, "ge r3 r3 LSL r2", "ge_r3_r3_LSL_r2"},
302 {{ge, r0, r0, ROR, r5}, true, ge, "ge r0 r0 ROR r5", "ge_r0_r0_ROR_r5"},
344 {{ge, r5, r5, ASR, r7}, true, ge, "ge r5 r5 ASR r7", "ge_r5_r5_ASR_r7"},
379 {{ge, r1, r1, ROR, r3}, true, ge, "ge r1 r1 ROR r3", "ge_r1_r1_ROR_r3"},
419 {{ge, r6, r6, LSR, r5}, true, ge, "ge r6 r6 LSR r5", "ge_r6_r6_LSR_r5"},
438 {{ge, r1, r1, ASR, r5}, true, ge, "ge r1 r1 ASR r5", "ge_r1_r1_ASR_r5"},
450 {{ge, r2, r2, ROR, r7}, true, ge, "ge r2 r2 ROR r7", "ge_r2_r2_ROR_r7"},
455 {{ge, r4, r4, LSL, r1}, true, ge, "ge r4 r4 LSL r1", "ge_r4_r4_LSL_r1"},
461 {{ge, r7, r7, LSR, r2}, true, ge, "ge r7 r7 LSR r2", "ge_r7_r7_LSR_r2"},
465 {{ge, r7, r7, ASR, r1}, true, ge, "ge r7 r7 ASR r1", "ge_r7_r7_ASR_r1"},
468 {{ge, r6, r6, LSL, r7}, true, ge, "ge r6 r6 LSL r7", "ge_r6_r6_LSL_r7"},
473 {{ge, r7, r7, LSL, r2}, true, ge, "ge r7 r7 LSL r2", "ge_r7_r7_LSL_r2"},
505 {{ge, r3, r3, LSR, r5}, true, ge, "ge r3 r3 LSR r5", "ge_r3_r3_LSR_r5"},
524 {{ge, r7, r7, LSL, r5}, true, ge, "ge r7 r7 LSL r5", "ge_r7_r7_LSL_r5"},
537 {{ge, r3, r3, ASR, r4}, true, ge, "ge r3 r3 ASR r4", "ge_r3_r3_ASR_r4"},
549 {{ge, r5, r5, ROR, r2}, true, ge, "ge r5 r5 ROR r2", "ge_r5_r5_ROR_r2"},
561 {{ge, r0, r0, ASR, r2}, true, ge, "ge r0 r0 ASR r2", "ge_r0_r0_ASR_r2"},
578 {{ge, r0, r0, ASR, r0}, true, ge, "ge r0 r0 ASR r0", "ge_r0_r0_ASR_r0"},
582 {{ge, r1, r1, LSR, r3}, true, ge, "ge r1 r1 LSR r3", "ge_r1_r1_LSR_r3"},
583 {{ge, r4, r4, ROR, r5}, true, ge, "ge r4 r4 ROR r5", "ge_r4_r4_ROR_r5"},
586 {{ge, r6, r6, LSR, r6}, true, ge, "ge r6 r6 LSR r6", "ge_r6_r6_LSR_r6"},
591 {{ge, r3, r3, LSR, r6}, true, ge, "ge r3 r3 LSR r6", "ge_r3_r3_LSR_r6"},
616 {{ge, r5, r5, ROR, r4}, true, ge, "ge r5 r5 ROR r4", "ge_r5_r5_ROR_r4"},
678 {{ge, r1, r1, LSL, r5}, true, ge, "ge r1 r1 LSL r5", "ge_r1_r1_LSL_r5"},
694 {{ge, r2, r2, ASR, r7}, true, ge, "ge r2 r2 ASR r7", "ge_r2_r2_ASR_r7"},
708 {{ge, r3, r3, LSR, r1}, true, ge, "ge r3 r3 LSR r1", "ge_r3_r3_LSR_r1"},
736 {{ge, r0, r0, ROR, r3}, true, ge, "ge r0 r0 ROR r3", "ge_r0_r0_ROR_r3"},
739 {{ge, r2, r2, ROR, r1}, true, ge, "ge r2 r2 ROR r1", "ge_r2_r2_ROR_r1"},
740 {{ge, r5, r5, LSR, r3}, true, ge, "ge r5 r5 LSR r3", "ge_r5_r5_LSR_r3"},
755 {{ge, r2, r2, LSR, r2}, true, ge, "ge r2 r2 LSR r2", "ge_r2_r2_LSR_r2"},
760 {{ge, r6, r6, ASR, r6}, true, ge, "ge r6 r6 ASR r6", "ge_r6_r6_ASR_r6"},
786 {{ge, r6, r6, ASR, r7}, true, ge, "ge r6 r6 ASR r7", "ge_r6_r6_ASR_r7"},
798 {{ge, r0, r0, ASR, r1}, true, ge, "ge r0 r0 ASR r1", "ge_r0_r0_ASR_r1"},
845 {{ge, r3, r3, ASR, r0}, true, ge, "ge r3 r3 ASR r0", "ge_r3_r3_ASR_r0"},
858 {{ge, r1, r1, LSR, r7}, true, ge, "ge r1 r1 LSR r7", "ge_r1_r1_LSR_r7"},
894 {{ge, r7, r7, LSR, r3}, true, ge, "ge r7 r7 LSR r3", "ge_r7_r7_LSR_r3"},
907 {{ge, r0, r0, LSR, r3}, true, ge, "ge r0 r0 LSR r3", "ge_r0_r0_LSR_r3"},
913 {{ge, r5, r5, LSL, r3}, true, ge, "ge r5 r5 LSL r3", "ge_r5_r5_LSL_r3"},
959 {{ge, r0, r0, LSR, r2}, true, ge, "ge r0 r0 LSR r2", "ge_r0_r0_LSR_r2"},
968 {{ge, r1, r1, ROR, r1}, true, ge, "ge r1 r1 ROR r1", "ge_r1_r1_ROR_r1"},
985 {{ge, r7, r7, ROR, r5}, true, ge, "ge r7 r7 ROR r5", "ge_r7_r7_ROR_r5"},
1001 {{ge, r3, r3, ROR, r4}, true, ge, "ge r3 r3 ROR r4", "ge_r3_r3_ROR_r4"},
1003 {{ge, r2, r2, LSL, r6}, true, ge, "ge r2 r2 LSL r6", "ge_r2_r2_LSL_r6"},
1020 {{ge, r0, r0, ASR, r5}, true, ge, "ge r0 r0 ASR r5", "ge_r0_r0_ASR_r5"},
1037 {{ge, r4, r4, ROR, r0}, true, ge, "ge r4 r4 ROR r0", "ge_r4_r4_ROR_r0"},
1040 {{ge, r5, r5, ROR, r1}, true, ge, "ge r5 r5 ROR r1", "ge_r5_r5_ROR_r1"},
1049 {{ge, r0, r0, ASR, r4}, true, ge, "ge r0 r0 ASR r4", "ge_r0_r0_ASR_r4"},
1060 {{ge, r1, r1, LSR, r2}, true, ge, "ge r1 r1 LSR r2", "ge_r1_r1_LSR_r2"},
1061 {{ge, r4, r4, LSR, r4}, true, ge, "ge r4 r4 LSR r4", "ge_r4_r4_LSR_r4"},
1076 {{ge, r0, r0, LSL, r5}, true, ge, "ge r0 r0 LSL r5", "ge_r0_r0_LSL_r5"},
1087 {{ge, r6, r6, ASR, r5}, true, ge, "ge r6 r6 ASR r5", "ge_r6_r6_ASR_r5"},
1092 {{ge, r0, r0, ROR, r4}, true, ge, "ge r0 r0 ROR r4", "ge_r0_r0_ROR_r4"},
1099 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-rs-in-it-block-mov-t32.h"
1118 // Values to pass to the macro-assembler. in TestHelper()
1139 masm.GetBuffer()->GetOffsetAddress<const byte*>(start); in TestHelper()
1141 uint32_t result_size = end - start; in TestHelper()
1216 total_error_count - kErrorReportLimit); in TestHelper()