Lines Matching refs:dup_immediate
542 LogicVRegister imm_reg = dup_immediate(vform, temp, imm); in cmp()
1492 LogicVRegister shiftreg = dup_immediate(vform, temp, shift); in shl()
1503 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); in sshll()
1515 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); in sshll2()
1543 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); in ushll()
1555 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); in ushll2()
1673 LogicVRegister shiftreg = dup_immediate(vform, temp, shift); in sqshl()
1684 LogicVRegister shiftreg = dup_immediate(vform, temp, shift); in uqshl()
1695 LogicVRegister shiftreg = dup_immediate(vform, temp, shift); in sqshlu()
1732 LogicVRegister shiftreg = dup_immediate(vform, temp, -shift); in ushr()
1743 LogicVRegister shiftreg = dup_immediate(vform, temp, -shift); in sshr()
2939 LogicVRegister Simulator::dup_immediate(VectorFormat vform, in dup_immediate() function in vixl::aarch64::Simulator
3032 dup_immediate(vform, zero, 0); in mov_zeroing()
5165 dup_immediate(vform, temp, Float16ToRawbits(SimFloat16(0.0))); in fcmp_zero()
5168 LogicVRegister zero_reg = dup_immediate(vform, temp, FloatToRawbits(0.0)); in fcmp_zero()
5172 LogicVRegister zero_reg = dup_immediate(vform, temp, DoubleToRawbits(0.0)); in fcmp_zero()
6585 dup_immediate(kFormatVnB, zero, 0); in FTMaddHelper()
6589 dup_immediate(vform, cf, coeff_pos); in FTMaddHelper()
6590 dup_immediate(vform, cfn, coeff_neg); in FTMaddHelper()