Lines Matching +defs:val +defs:src
87 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble()
98 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble()
114 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat()
125 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) { in UFixedToFloat()
141 SimFloat16 Simulator::FixedToFloat16(int64_t src, int fbits, FPRounding round) { in FixedToFloat16()
152 SimFloat16 Simulator::UFixedToFloat16(uint64_t src, in UFixedToFloat16()
380 void Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) { in st1()
389 LogicVRegister src, in st1()
397 LogicVRegister src, in st2()
412 LogicVRegister src, in st2()
423 LogicVRegister src, in st3()
442 LogicVRegister src, in st3()
455 LogicVRegister src, in st4()
478 LogicVRegister src, in st4()
1074 const LogicVRegister& src, in bic()
1182 const LogicVRegister* src = &src1; in sminmaxp() local
1224 const LogicVRegister& src) { in addp()
1236 const LogicVRegister& src) { in addv()
1254 const LogicVRegister& src) { in saddlv()
1271 const LogicVRegister& src) { in uaddlv()
1289 const LogicVRegister& src, in sminmaxv()
1310 const LogicVRegister& src) { in smaxv()
1318 const LogicVRegister& src) { in sminv()
1327 const LogicVRegister& src) { in smaxv()
1337 const LogicVRegister& src) { in sminv()
1388 const LogicVRegister* src = &src1; in uminmaxp() local
1431 const LogicVRegister& src, in uminmaxv()
1452 const LogicVRegister& src) { in umaxv()
1460 const LogicVRegister& src) { in uminv()
1469 const LogicVRegister& src) { in umaxv()
1479 const LogicVRegister& src) { in uminv()
1488 const LogicVRegister& src, in shl()
1499 const LogicVRegister& src, in sshll()
1511 const LogicVRegister& src, in sshll2()
1523 const LogicVRegister& src) { in shll()
1531 const LogicVRegister& src) { in shll2()
1539 const LogicVRegister& src, in ushll()
1551 const LogicVRegister& src, in ushll2()
1562 const LogicVRegister& src, in clast()
1577 const LogicVRegister& src) { in compact()
1652 const LogicVRegister& src, in sli()
1669 const LogicVRegister& src, in sqshl()
1680 const LogicVRegister& src, in uqshl()
1691 const LogicVRegister& src, in sqshlu()
1702 const LogicVRegister& src, in sri()
1728 const LogicVRegister& src, in ushr()
1739 const LogicVRegister& src, in sshr()
1750 const LogicVRegister& src, in ssra()
1760 const LogicVRegister& src, in usra()
1770 const LogicVRegister& src, in srsra()
1780 const LogicVRegister& src, in ursra()
1790 const LogicVRegister& src) { in cls()
1811 const LogicVRegister& src) { in clz()
1832 const LogicVRegister& src) { in cnot()
1844 const LogicVRegister& src) { in cnt()
2009 const LogicVRegister& src) { in neg()
2069 const LogicVRegister& src) { in abs()
2090 const LogicVRegister& src) { in andv()
2109 const LogicVRegister& src) { in eorv()
2128 const LogicVRegister& src) { in orv()
2147 const LogicVRegister& src) { in saddv()
2169 const LogicVRegister& src) { in uaddv()
2187 const LogicVRegister& src, in extractnarrow()
2251 const LogicVRegister& src) { in xtn()
2258 const LogicVRegister& src) { in sqxtn()
2265 const LogicVRegister& src) { in sqxtun()
2272 const LogicVRegister& src) { in uqxtn()
2324 const LogicVRegister& src) { in not_()
2335 const LogicVRegister& src) { in rbit()
2361 const LogicVRegister& src) { in rev()
2375 const LogicVRegister& src, in rev_byte()
2396 const LogicVRegister& src) { in rev16()
2403 const LogicVRegister& src) { in rev32()
2410 const LogicVRegister& src) { in rev64()
2416 const LogicVRegister& src, in addlp()
2447 const LogicVRegister& src) { in saddlp()
2454 const LogicVRegister& src) { in uaddlp()
2461 const LogicVRegister& src) { in sadalp()
2468 const LogicVRegister& src) { in uadalp()
2474 const LogicVRegister& src, in ror()
2506 const LogicVRegister& src, in rotate_elements_right()
2519 const LogicVRegister& src) { in fadda()
2536 const LogicVRegister& src) { in fadda()
2880 const LogicVRegister& src, in dup_element()
2907 const LogicVRegister& src, in dup_elements_to_segments()
2955 const LogicVRegister& src, in ins_element()
3000 const LogicVRegister& src) { in mov()
3009 LogicPRegister Simulator::mov(LogicPRegister dst, const LogicPRegister& src) { in mov()
3023 const LogicVRegister& src) { in mov_merging()
3030 const LogicVRegister& src) { in mov_zeroing()
3038 const LogicVRegister& src, in mov_alternating()
3049 const LogicPRegister& src) { in mov_merging()
3055 const LogicPRegister& src) { in mov_zeroing()
3086 const LogicVRegister& src, in orr()
3103 const LogicVRegister& src, in uxtl()
3119 const LogicVRegister& src, in sxtl()
3135 const LogicVRegister& src) { in uxtl2()
3142 const LogicVRegister& src) { in sxtl2()
3149 const LogicVRegister& src, in uxt()
3164 const LogicVRegister& src, in sxt()
3180 const LogicVRegister& src, in shrn()
3192 const LogicVRegister& src, in shrn2()
3204 const LogicVRegister& src, in rshrn()
3216 const LogicVRegister& src, in rshrn2()
3336 const LogicVRegister& src, in uqshrn()
3344 const LogicVRegister& src, in uqshrn2()
3352 const LogicVRegister& src, in uqrshrn()
3360 const LogicVRegister& src, in uqrshrn2()
3368 const LogicVRegister& src, in sqshrn()
3380 const LogicVRegister& src, in sqshrn2()
3392 const LogicVRegister& src, in sqrshrn()
3404 const LogicVRegister& src, in sqrshrn2()
3416 const LogicVRegister& src, in sqshrun()
3428 const LogicVRegister& src, in sqshrun2()
3440 const LogicVRegister& src, in sqrshrun()
3452 const LogicVRegister& src, in sqrshrun2()
4431 const LogicVRegister& src) { in interleave_top_bottom()
5160 const LogicVRegister& src, in fcmp_zero()
5297 int src = i + LaneCountFromFormat(vform); in fmlal2() local
5332 int src = i + LaneCountFromFormat(vform); in fmlsl2() local
5370 int src = i + LaneCountFromFormat(vform); in fmlal2() local
5407 int src = i + LaneCountFromFormat(vform); in fmlsl2() local
5420 const LogicVRegister& src) { in fneg()
5433 const LogicVRegister& src) { in fneg()
5449 const LogicVRegister& src) { in fabs_()
5464 const LogicVRegister& src) { in fabs_()
5490 const LogicVRegister& src) { in fsqrt()
5580 const LogicVRegister& src, in FPPairedAcrossHelper()
5606 const LogicVRegister& src) { in faddv()
5618 const LogicVRegister& src) { in fmaxv()
5634 const LogicVRegister& src) { in fminv()
5650 const LogicVRegister& src) { in fmaxnmv()
5665 const LogicVRegister& src) { in fminnmv()
5768 const LogicVRegister& src, in frint()
5811 const LogicVRegister& src) { in fcvt()
5840 const LogicVRegister& src, in fcvts()
5876 const LogicVRegister& src, in fcvts()
5895 const LogicVRegister& src, in fcvtu()
5931 const LogicVRegister& src, in fcvtu()
5947 const LogicVRegister& src) { in fcvtl()
5967 const LogicVRegister& src) { in fcvtl2()
5989 const LogicVRegister& src) { in fcvtn()
6012 const LogicVRegister& src) { in fcvtn2()
6033 const LogicVRegister& src) { in fcvtxn()
6054 const LogicVRegister& src) { in fcvtxn2()
6081 static inline uint64_t Bits(uint64_t val, int start_bit, int end_bit) { in Bits()
6163 const LogicVRegister& src) { in frsqrte()
6307 const LogicVRegister& src, in frecpe()
6333 const LogicVRegister& src) { in ursqrte()
6366 const LogicVRegister& src) { in urecpe()
6392 const LogicPRegister& src) { in pfirst()
6413 const LogicPRegister& src) { in pnext()
6429 const LogicVRegister& src) { in frecpx()
6465 const LogicVRegister& src) { in frecpx()
6479 const LogicVRegister& src) { in flogb()
6701 const LogicVRegister& src) { in fexpa()
6828 const LogicVRegister& src, in scvtf()
6869 const LogicVRegister& src, in scvtf()
6887 const LogicVRegister& src, in ucvtf()
6928 const LogicVRegister& src, in ucvtf()
6943 const LogicVRegister& src, in unpk()
7680 const LogicVRegister& src) { in pack_odd_elements()
7688 const LogicVRegister& src) { in pack_even_elements()