1956     Register rm = operand.GetBaseRegister();  in adc()  local
1959         // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in adc()
1961             rm.IsLow()) {  in adc()
1962           EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3));  in adc()
1971       // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in adc()
1973           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in adc()
1976                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in adc()
1982       // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in adc()
1986                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adc()
1993     Register rm = operand.GetBaseRegister();  in adc()  local
1997       // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in adc()
1999           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in adc()
2002                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adc()
2044     Register rm = operand.GetBaseRegister();  in adcs()  local
2047         // ADCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in adcs()
2049             rm.IsLow()) {  in adcs()
2050           EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3));  in adcs()
2059       // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in adcs()
2061           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in adcs()
2064                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in adcs()
2070       // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in adcs()
2074                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adcs()
2081     Register rm = operand.GetBaseRegister();  in adcs()  local
2085       // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in adcs()
2087           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in adcs()
2090                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adcs()
2217     Register rm = operand.GetBaseRegister();  in add()  local
2220         // ADD<c>{<q>} <Rd>, <Rn>, <Rm> ; T1  in add()
2222             rm.IsLow()) {  in add()
2224                      (rm.GetCode() << 6));  in add()
2228         // ADD{<c>}{<q>} {<Rdn>}, <Rdn>, <Rm> ; T2  in add()
2229         if (!size.IsWide() && rd.Is(rn) && !rm.Is(sp) &&  in add()
2231               (!rd.IsPC() || !rm.IsPC())) ||  in add()
2234                      ((rd.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));  in add()
2239         if (!size.IsWide() && rd.Is(rm) && rn.Is(sp) &&  in add()
2247         // ADD{<c>}{<q>} {SP}, SP, <Rm> ; T2  in add()
2248         if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && !rm.Is(sp)) {  in add()
2249           EmitT32_16(0x4485 | (rm.GetCode() << 3));  in add()
2258       // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3  in add()
2260           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in add()
2263                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in add()
2268       // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3  in add()
2270           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in add()
2272         EmitT32_32(0xeb0d0000U | (rd.GetCode() << 8) | rm.GetCode() |  in add()
2279       // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in add()
2283                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in add()
2287       // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1  in add()
2291                 (rd.GetCode() << 12) | rm.GetCode() |  in add()
2298     Register rm = operand.GetBaseRegister();  in add()  local
2302       // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in add()
2304           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in add()
2307                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in add()
2331     Register rm = operand.GetBaseRegister();  in add()  local
2333       // ADD<c>{<q>} <Rdn>, <Rm> ; T2  in add()
2334       if (InITBlock() && !rm.Is(sp) &&  in add()
2336             (!rd.IsPC() || !rm.IsPC())) ||  in add()
2339                    (rm.GetCode() << 3));  in add()
2411     Register rm = operand.GetBaseRegister();  in adds()  local
2414         // ADDS{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in adds()
2416             rm.IsLow()) {  in adds()
2418                      (rm.GetCode() << 6));  in adds()
2427       // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3  in adds()
2429           !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in adds()
2432                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in adds()
2437       // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3  in adds()
2439           !rd.Is(pc) && (!rm.IsPC() || AllowUnpredictable())) {  in adds()
2441         EmitT32_32(0xeb1d0000U | (rd.GetCode() << 8) | rm.GetCode() |  in adds()
2448       // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in adds()
2452                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adds()
2456       // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1  in adds()
2460                 (rd.GetCode() << 12) | rm.GetCode() |  in adds()
2467     Register rm = operand.GetBaseRegister();  in adds()  local
2471       // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in adds()
2473           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in adds()
2476                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adds()
2730     Register rm = operand.GetBaseRegister();  in and_()  local
2733         // AND<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in and_()
2735             rm.IsLow()) {  in and_()
2736           EmitT32_16(0x4000 | rd.GetCode() | (rm.GetCode() << 3));  in and_()
2745       // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in and_()
2747           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in and_()
2750                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in and_()
2756       // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in and_()
2760                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in and_()
2767     Register rm = operand.GetBaseRegister();  in and_()  local
2771       // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in and_()
2773           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in and_()
2776                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in and_()
2818     Register rm = operand.GetBaseRegister();  in ands()  local
2821         // ANDS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in ands()
2823             rm.IsLow()) {  in ands()
2824           EmitT32_16(0x4000 | rd.GetCode() | (rm.GetCode() << 3));  in ands()
2833       // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in ands()
2835           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ands()
2838                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in ands()
2844       // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in ands()
2848                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ands()
2855     Register rm = operand.GetBaseRegister();  in ands()  local
2859       // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in ands()
2861           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in ands()
2864                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ands()
2876                     Register rm,  in asr()  argument
2883       // ASR<c>{<q>} {<Rd>}, <Rm>, #<imm> ; T2  in asr()
2884       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in asr()
2887         EmitT32_16(0x1000 | rd.GetCode() | (rm.GetCode() << 3) |  in asr()
2892       // ASR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3  in asr()
2894           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in asr()
2896         EmitT32_32(0xea4f0020U | (rd.GetCode() << 8) | rm.GetCode() |  in asr()
2902       // ASR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1  in asr()
2906                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));  in asr()
2915       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in asr()
2921       // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2  in asr()
2923           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in asr()
2924         EmitT32_32(0xfa40f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in asr()
2930       // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1  in asr()
2932           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in asr()
2934                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in asr()
2939   Delegate(kAsr, &Assembler::asr, cond, size, rd, rm, operand);  in asr()
2945                      Register rm,  in asrs()  argument
2952       // ASRS{<q>} {<Rd>}, <Rm>, #<imm> ; T2  in asrs()
2953       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in asrs()
2956         EmitT32_16(0x1000 | rd.GetCode() | (rm.GetCode() << 3) |  in asrs()
2961       // ASRS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3  in asrs()
2963           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in asrs()
2965         EmitT32_32(0xea5f0020U | (rd.GetCode() << 8) | rm.GetCode() |  in asrs()
2971       // ASRS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1  in asrs()
2975                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));  in asrs()
2984       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in asrs()
2990       // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2  in asrs()
2992           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in asrs()
2993         EmitT32_32(0xfa50f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in asrs()
2999       // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1  in asrs()
3001           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in asrs()
3003                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in asrs()
3008   Delegate(kAsrs, &Assembler::asrs, cond, size, rd, rm, operand);  in asrs()
3283     Register rm = operand.GetBaseRegister();  in bic()  local
3286         // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in bic()
3288             rm.IsLow()) {  in bic()
3289           EmitT32_16(0x4380 | rd.GetCode() | (rm.GetCode() << 3));  in bic()
3298       // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in bic()
3300           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in bic()
3303                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in bic()
3309       // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in bic()
3313                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in bic()
3320     Register rm = operand.GetBaseRegister();  in bic()  local
3324       // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in bic()
3326           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in bic()
3329                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in bic()
3371     Register rm = operand.GetBaseRegister();  in bics()  local
3374         // BICS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in bics()
3376             rm.IsLow()) {  in bics()
3377           EmitT32_16(0x4380 | rd.GetCode() | (rm.GetCode() << 3));  in bics()
3386       // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in bics()
3388           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in bics()
3391                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in bics()
3397       // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in bics()
3401                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in bics()
3408     Register rm = operand.GetBaseRegister();  in bics()  local
3412       // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in bics()
3414           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in bics()
3417                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in bics()
3622 void Assembler::blx(Condition cond, Register rm) {  in blx()  argument
3626     // BLX{<c>}{<q>} <Rm> ; T1  in blx()
3627     if (((!rm.IsPC() && OutsideITBlockAndAlOrLast(cond)) ||  in blx()
3629       EmitT32_16(0x4780 | (rm.GetCode() << 3));  in blx()
3634     // BLX{<c>}{<q>} <Rm> ; A1  in blx()
3635     if (cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {  in blx()
3636       EmitA32(0x012fff30U | (cond.GetCondition() << 28) | rm.GetCode());  in blx()
3640   Delegate(kBlx, &Assembler::blx, cond, rm);  in blx()
3643 void Assembler::bx(Condition cond, Register rm) {  in bx()  argument
3647     // BX{<c>}{<q>} <Rm> ; T1  in bx()
3649       EmitT32_16(0x4700 | (rm.GetCode() << 3));  in bx()
3654     // BX{<c>}{<q>} <Rm> ; A1  in bx()
3656       EmitA32(0x012fff10U | (cond.GetCondition() << 28) | rm.GetCode());  in bx()
3660   Delegate(kBx, &Assembler::bx, cond, rm);  in bx()
3663 void Assembler::bxj(Condition cond, Register rm) {  in bxj()  argument
3667     // BXJ{<c>}{<q>} <Rm> ; T1  in bxj()
3668     if (((!rm.IsPC() && OutsideITBlockAndAlOrLast(cond)) ||  in bxj()
3670       EmitT32_32(0xf3c08f00U | (rm.GetCode() << 16));  in bxj()
3675     // BXJ{<c>}{<q>} <Rm> ; A1  in bxj()
3676     if (cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {  in bxj()
3677       EmitA32(0x012fff20U | (cond.GetCondition() << 28) | rm.GetCode());  in bxj()
3681   Delegate(kBxj, &Assembler::bxj, cond, rm);  in bxj()
3800 void Assembler::clz(Condition cond, Register rd, Register rm) {  in clz()  argument
3804     // CLZ{<c>}{<q>} <Rd>, <Rm> ; T1  in clz()
3805     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in clz()
3806       EmitT32_32(0xfab0f080U | (rd.GetCode() << 8) | rm.GetCode() |  in clz()
3807                  (rm.GetCode() << 16));  in clz()
3812     // CLZ{<c>}{<q>} <Rd>, <Rm> ; A1  in clz()
3814         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in clz()
3816               rm.GetCode());  in clz()
3820   Delegate(kClz, &Assembler::clz, cond, rd, rm);  in clz()
3854     Register rm = operand.GetBaseRegister();  in cmn()  local
3857         // CMN{<c>}{<q>} <Rn>, <Rm> ; T1  in cmn()
3858         if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {  in cmn()
3859           EmitT32_16(0x42c0 | rn.GetCode() | (rm.GetCode() << 3));  in cmn()
3868       // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T2  in cmn()
3870           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in cmn()
3872         EmitT32_32(0xeb100f00U | (rn.GetCode() << 16) | rm.GetCode() |  in cmn()
3879       // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1  in cmn()
3883                 (rn.GetCode() << 16) | rm.GetCode() |  in cmn()
3890     Register rm = operand.GetBaseRegister();  in cmn()  local
3894       // CMN{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1  in cmn()
3896           ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in cmn()
3898                 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |  in cmn()
3944     Register rm = operand.GetBaseRegister();  in cmp()  local
3947         // CMP{<c>}{<q>} <Rn>, <Rm> ; T1  in cmp()
3948         if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {  in cmp()
3949           EmitT32_16(0x4280 | rn.GetCode() | (rm.GetCode() << 3));  in cmp()
3953         // CMP{<c>}{<q>} <Rn>, <Rm> ; T2  in cmp()
3955             ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in cmp()
3957                      ((rn.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));  in cmp()
3966       // CMP{<c>}{<q>} <Rn>, <Rm>, <shift> #<amount> ; T3  in cmp()
3968           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in cmp()
3970         EmitT32_32(0xebb00f00U | (rn.GetCode() << 16) | rm.GetCode() |  in cmp()
3977       // CMP{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1  in cmp()
3981                 (rn.GetCode() << 16) | rm.GetCode() |  in cmp()
3988     Register rm = operand.GetBaseRegister();  in cmp()  local
3992       // CMP{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1  in cmp()
3994           ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in cmp()
3996                 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |  in cmp()
4005 void Assembler::crc32b(Condition cond, Register rd, Register rn, Register rm) {  in crc32b()  argument
4009     // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; T1  in crc32b()
4010     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32b()
4013                  rm.GetCode());  in crc32b()
4018     // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; A1  in crc32b()
4020         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32b()
4022               (rn.GetCode() << 16) | rm.GetCode());  in crc32b()
4026   Delegate(kCrc32b, &Assembler::crc32b, cond, rd, rn, rm);  in crc32b()
4029 void Assembler::crc32cb(Condition cond, Register rd, Register rn, Register rm) {  in crc32cb()  argument
4033     // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; T1  in crc32cb()
4034     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32cb()
4037                  rm.GetCode());  in crc32cb()
4042     // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; A1  in crc32cb()
4044         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32cb()
4046               (rn.GetCode() << 16) | rm.GetCode());  in crc32cb()
4050   Delegate(kCrc32cb, &Assembler::crc32cb, cond, rd, rn, rm);  in crc32cb()
4053 void Assembler::crc32ch(Condition cond, Register rd, Register rn, Register rm) {  in crc32ch()  argument
4057     // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; T1  in crc32ch()
4058     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32ch()
4061                  rm.GetCode());  in crc32ch()
4066     // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; A1  in crc32ch()
4068         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32ch()
4070               (rn.GetCode() << 16) | rm.GetCode());  in crc32ch()
4074   Delegate(kCrc32ch, &Assembler::crc32ch, cond, rd, rn, rm);  in crc32ch()
4077 void Assembler::crc32cw(Condition cond, Register rd, Register rn, Register rm) {  in crc32cw()  argument
4081     // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; T1  in crc32cw()
4082     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32cw()
4085                  rm.GetCode());  in crc32cw()
4090     // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; A1  in crc32cw()
4092         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32cw()
4094               (rn.GetCode() << 16) | rm.GetCode());  in crc32cw()
4098   Delegate(kCrc32cw, &Assembler::crc32cw, cond, rd, rn, rm);  in crc32cw()
4101 void Assembler::crc32h(Condition cond, Register rd, Register rn, Register rm) {  in crc32h()  argument
4105     // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; T1  in crc32h()
4106     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32h()
4109                  rm.GetCode());  in crc32h()
4114     // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; A1  in crc32h()
4116         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32h()
4118               (rn.GetCode() << 16) | rm.GetCode());  in crc32h()
4122   Delegate(kCrc32h, &Assembler::crc32h, cond, rd, rn, rm);  in crc32h()
4125 void Assembler::crc32w(Condition cond, Register rd, Register rn, Register rm) {  in crc32w()  argument
4129     // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; T1  in crc32w()
4130     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32w()
4133                  rm.GetCode());  in crc32w()
4138     // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; A1  in crc32w()
4140         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32w()
4142               (rn.GetCode() << 16) | rm.GetCode());  in crc32w()
4146   Delegate(kCrc32w, &Assembler::crc32w, cond, rd, rn, rm);  in crc32w()
4218     Register rm = operand.GetBaseRegister();  in eor()  local
4221         // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in eor()
4223             rm.IsLow()) {  in eor()
4224           EmitT32_16(0x4040 | rd.GetCode() | (rm.GetCode() << 3));  in eor()
4233       // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in eor()
4235           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in eor()
4238                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in eor()
4244       // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in eor()
4248                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in eor()
4255     Register rm = operand.GetBaseRegister();  in eor()  local
4259       // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in eor()
4261           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in eor()
4264                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in eor()
4306     Register rm = operand.GetBaseRegister();  in eors()  local
4309         // EORS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in eors()
4311             rm.IsLow()) {  in eors()
4312           EmitT32_16(0x4040 | rd.GetCode() | (rm.GetCode() << 3));  in eors()
4321       // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in eors()
4323           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in eors()
4326                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in eors()
4332       // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in eors()
4336                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in eors()
4343     Register rm = operand.GetBaseRegister();  in eors()  local
4347       // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in eors()
4349           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in eors()
4352                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in eors()
5120     Register rm = operand.GetOffsetRegister();  in ldr()  local
5122       // LDR{<c>}{<q>} <Rt>, [<Rn>, #{+}<Rm>] ; T1  in ldr()
5123       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldr()
5126                    (rm.GetCode() << 6));  in ldr()
5135     Register rm = operand.GetOffsetRegister();  in ldr()  local
5139       // LDR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}] ; T2  in ldr()
5142           ((!rm.IsPC() && (!rt.IsPC() || OutsideITBlockAndAlOrLast(cond))) ||  in ldr()
5145                    rm.GetCode() | (amount << 4));  in ldr()
5150       // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1  in ldr()
5152           (!rm.IsPC() || AllowUnpredictable())) {  in ldr()
5157                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldr()
5161       // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1  in ldr()
5163           cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {  in ldr()
5168                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldr()
5172       // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1  in ldr()
5174           (!rm.IsPC() || AllowUnpredictable())) {  in ldr()
5179                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldr()
5423     Register rm = operand.GetOffsetRegister();  in ldrb()  local
5425       // LDRB{<c>}{<q>} <Rt>, [<Rn>, #{+}<Rm>] ; T1  in ldrb()
5426       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldrb()
5429                    (rm.GetCode() << 6));  in ldrb()
5438     Register rm = operand.GetOffsetRegister();  in ldrb()  local
5442       // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}] ; T2  in ldrb()
5445           (!rm.IsPC() || AllowUnpredictable())) {  in ldrb()
5447                    rm.GetCode() | (amount << 4));  in ldrb()
5452       // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1  in ldrb()
5454           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrb()
5459                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrb()
5463       // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1  in ldrb()
5466           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrb()
5471                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrb()
5475       // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1  in ldrb()
5477           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrb()
5482                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrb()
5691     Register rm = operand.GetOffsetRegister();  in ldrd()  local
5693       // LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<Rm>] ; A1  in ldrd()
5696           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in ldrd()
5700                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrd()
5704       // LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<Rm> ; A1  in ldrd()
5707           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in ldrd()
5711                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrd()
5715       // LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<Rm>]! ; A1  in ldrd()
5718           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in ldrd()
5722                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrd()
6057     Register rm = operand.GetOffsetRegister();  in ldrh()  local
6059       // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+}<Rm>] ; T1  in ldrh()
6060       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldrh()
6063                    (rm.GetCode() << 6));  in ldrh()
6068       // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1  in ldrh()
6070           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrh()
6073                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrh()
6077       // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1  in ldrh()
6079           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrh()
6082                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrh()
6086       // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1  in ldrh()
6088           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrh()
6091                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrh()
6100     Register rm = operand.GetOffsetRegister();  in ldrh()  local
6104       // LDRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}] ; T2  in ldrh()
6107           (!rm.IsPC() || AllowUnpredictable())) {  in ldrh()
6109                    rm.GetCode() | (amount << 4));  in ldrh()
6312     Register rm = operand.GetOffsetRegister();  in ldrsb()  local
6314       // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+}<Rm>] ; T1  in ldrsb()
6315       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldrsb()
6318                    (rm.GetCode() << 6));  in ldrsb()
6323       // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1  in ldrsb()
6325           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsb()
6328                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsb()
6332       // LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1  in ldrsb()
6334           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsb()
6337                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsb()
6341       // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1  in ldrsb()
6343           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsb()
6346                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsb()
6355     Register rm = operand.GetOffsetRegister();  in ldrsb()  local
6359       // LDRSB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}] ; T2  in ldrsb()
6362           (!rm.IsPC() || AllowUnpredictable())) {  in ldrsb()
6364                    rm.GetCode() | (amount << 4));  in ldrsb()
6567     Register rm = operand.GetOffsetRegister();  in ldrsh()  local
6569       // LDRSH{<c>}{<q>} <Rt>, [<Rn>, #{+}<Rm>] ; T1  in ldrsh()
6570       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldrsh()
6573                    (rm.GetCode() << 6));  in ldrsh()
6578       // LDRSH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1  in ldrsh()
6580           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsh()
6583                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsh()
6587       // LDRSH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1  in ldrsh()
6589           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsh()
6592                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsh()
6596       // LDRSH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1  in ldrsh()
6598           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsh()
6601                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsh()
6610     Register rm = operand.GetOffsetRegister();  in ldrsh()  local
6614       // LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}] ; T2  in ldrsh()
6617           (!rm.IsPC() || AllowUnpredictable())) {  in ldrsh()
6619                    rm.GetCode() | (amount << 4));  in ldrsh()
6720                     Register rm,  in lsl()  argument
6727       // LSL<c>{<q>} {<Rd>}, <Rm>, #<imm> ; T2  in lsl()
6728       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in lsl()
6730         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) | (imm << 6));  in lsl()
6734       // LSL{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3  in lsl()
6736           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in lsl()
6737         EmitT32_32(0xea4f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in lsl()
6743       // LSL{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1  in lsl()
6746                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));  in lsl()
6755       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in lsl()
6761       // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2  in lsl()
6763           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsl()
6764         EmitT32_32(0xfa00f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in lsl()
6770       // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1  in lsl()
6772           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsl()
6774                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in lsl()
6779   Delegate(kLsl, &Assembler::lsl, cond, size, rd, rm, operand);  in lsl()
6785                      Register rm,  in lsls()  argument
6792       // LSLS{<q>} {<Rd>}, <Rm>, #<imm> ; T2  in lsls()
6793       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in lsls()
6795         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) | (imm << 6));  in lsls()
6799       // LSLS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3  in lsls()
6801           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in lsls()
6802         EmitT32_32(0xea5f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in lsls()
6808       // LSLS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1  in lsls()
6811                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));  in lsls()
6820       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in lsls()
6826       // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2  in lsls()
6828           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsls()
6829         EmitT32_32(0xfa10f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in lsls()
6835       // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1  in lsls()
6837           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsls()
6839                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in lsls()
6844   Delegate(kLsls, &Assembler::lsls, cond, size, rd, rm, operand);  in lsls()
6850                     Register rm,  in lsr()  argument
6857       // LSR<c>{<q>} {<Rd>}, <Rm>, #<imm> ; T2  in lsr()
6858       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in lsr()
6861         EmitT32_16(0x0800 | rd.GetCode() | (rm.GetCode() << 3) |  in lsr()
6866       // LSR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3  in lsr()
6868           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in lsr()
6870         EmitT32_32(0xea4f0010U | (rd.GetCode() << 8) | rm.GetCode() |  in lsr()
6876       // LSR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1  in lsr()
6880                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));  in lsr()
6889       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in lsr()
6895       // LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2  in lsr()
6897           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsr()
6898         EmitT32_32(0xfa20f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in lsr()
6904       // LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1  in lsr()
6906           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsr()
6908                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in lsr()
6913   Delegate(kLsr, &Assembler::lsr, cond, size, rd, rm, operand);  in lsr()
6919                      Register rm,  in lsrs()  argument
6926       // LSRS{<q>} {<Rd>}, <Rm>, #<imm> ; T2  in lsrs()
6927       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in lsrs()
6930         EmitT32_16(0x0800 | rd.GetCode() | (rm.GetCode() << 3) |  in lsrs()
6935       // LSRS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3  in lsrs()
6937           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in lsrs()
6939         EmitT32_32(0xea5f0010U | (rd.GetCode() << 8) | rm.GetCode() |  in lsrs()
6945       // LSRS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1  in lsrs()
6949                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));  in lsrs()
6958       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in lsrs()
6964       // LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2  in lsrs()
6966           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsrs()
6967         EmitT32_32(0xfa30f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in lsrs()
6973       // LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1  in lsrs()
6975           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsrs()
6977                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in lsrs()
6982   Delegate(kLsrs, &Assembler::lsrs, cond, size, rd, rm, operand);  in lsrs()
6986     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in mla()  argument
6990     // MLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in mla()
6992         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mla()
6994                  rm.GetCode() | (ra.GetCode() << 12));  in mla()
6999     // MLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in mla()
7001         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in mla()
7004               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in mla()
7008   Delegate(kMla, &Assembler::mla, cond, rd, rn, rm, ra);  in mla()
7012     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in mlas()  argument
7016     // MLAS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in mlas()
7018         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in mlas()
7021               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in mlas()
7025   Delegate(kMlas, &Assembler::mlas, cond, rd, rn, rm, ra);  in mlas()
7029     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in mls()  argument
7033     // MLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in mls()
7034     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in mls()
7037                  rm.GetCode() | (ra.GetCode() << 12));  in mls()
7042     // MLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in mls()
7044         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in mls()
7047               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in mls()
7051   Delegate(kMls, &Assembler::mls, cond, rd, rn, rm, ra);  in mls()
7061     Register rm = operand.GetBaseRegister();  in mov()  local
7064         // MOV{<c>}{<q>} <Rd>, <Rm> ; T1  in mov()
7069                      ((rd.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));  in mov()
7078       // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2  in mov()
7080           shift.IsValidAmount(amount) && rm.IsLow() &&  in mov()
7084         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) |  in mov()
7089       // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3  in mov()
7091           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mov()
7093         EmitT32_32(0xea4f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in mov()
7100       // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1  in mov()
7104                 (rd.GetCode() << 12) | rm.GetCode() |  in mov()
7111     Register rm = operand.GetBaseRegister();  in mov()  local
7116       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in mov()
7123       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in mov()
7130       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in mov()
7137       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in mov()
7143       // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2  in mov()
7145           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in mov()
7146         EmitT32_32(0xfa00f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in mov()
7152       // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1  in mov()
7154           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in mov()
7156                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |  in mov()
7218     Register rm = operand.GetBaseRegister();  in movs()  local
7222       // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2  in movs()
7224           shift.IsValidAmount(amount) && rm.IsLow() &&  in movs()
7227         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) |  in movs()
7232       // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3  in movs()
7234           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in movs()
7236         EmitT32_32(0xea5f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in movs()
7243       // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1  in movs()
7248                 (rd.GetCode() << 12) | rm.GetCode() |  in movs()
7255     Register rm = operand.GetBaseRegister();  in movs()  local
7260       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in movs()
7267       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in movs()
7274       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in movs()
7281       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in movs()
7287       // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2  in movs()
7289           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in movs()
7290         EmitT32_32(0xfa10f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in movs()
7296       // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1  in movs()
7298           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in movs()
7300                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |  in movs()
7457     Condition cond, EncodingSize size, Register rd, Register rn, Register rm) {  in mul()  argument
7462     if (InITBlock() && !size.IsWide() && rd.Is(rm) && rn.IsLow() &&  in mul()
7463         rm.IsLow()) {  in mul()
7468     // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; T2  in mul()
7470         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mul()
7472                  rm.GetCode());  in mul()
7477     // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1  in mul()
7479         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mul()
7481               rn.GetCode() | (rm.GetCode() << 8));  in mul()
7485   Delegate(kMul, &Assembler::mul, cond, size, rd, rn, rm);  in mul()
7488 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) {  in muls()  argument
7493     if (OutsideITBlock() && rd.Is(rm) && rn.IsLow() && rm.IsLow()) {  in muls()
7499     // MULS{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1  in muls()
7501         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in muls()
7503               rn.GetCode() | (rm.GetCode() << 8));  in muls()
7507   Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm);  in muls()
7541     Register rm = operand.GetBaseRegister();  in mvn()  local
7544         // MVN<c>{<q>} <Rd>, <Rm> ; T1  in mvn()
7545         if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow()) {  in mvn()
7546           EmitT32_16(0x43c0 | rd.GetCode() | (rm.GetCode() << 3));  in mvn()
7555       // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2  in mvn()
7557           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mvn()
7559         EmitT32_32(0xea6f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in mvn()
7566       // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1  in mvn()
7570                 (rd.GetCode() << 12) | rm.GetCode() |  in mvn()
7577     Register rm = operand.GetBaseRegister();  in mvn()  local
7581       // MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1  in mvn()
7583           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in mvn()
7585                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |  in mvn()
7625     Register rm = operand.GetBaseRegister();  in mvns()  local
7628         // MVNS{<q>} <Rd>, <Rm> ; T1  in mvns()
7629         if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow()) {  in mvns()
7630           EmitT32_16(0x43c0 | rd.GetCode() | (rm.GetCode() << 3));  in mvns()
7639       // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2  in mvns()
7641           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mvns()
7643         EmitT32_32(0xea7f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in mvns()
7650       // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1  in mvns()
7654                 (rd.GetCode() << 12) | rm.GetCode() |  in mvns()
7661     Register rm = operand.GetBaseRegister();  in mvns()  local
7665       // MVNS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1  in mvns()
7667           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in mvns()
7669                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |  in mvns()
7727     Register rm = operand.GetBaseRegister();  in orn()  local
7731       // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1  in orn()
7733           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in orn()
7736                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in orn()
7769     Register rm = operand.GetBaseRegister();  in orns()  local
7773       // ORNS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1  in orns()
7775           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in orns()
7778                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in orns()
7821     Register rm = operand.GetBaseRegister();  in orr()  local
7824         // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in orr()
7826             rm.IsLow()) {  in orr()
7827           EmitT32_16(0x4300 | rd.GetCode() | (rm.GetCode() << 3));  in orr()
7836       // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in orr()
7838           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in orr()
7841                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in orr()
7847       // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in orr()
7851                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in orr()
7858     Register rm = operand.GetBaseRegister();  in orr()  local
7862       // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in orr()
7864           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in orr()
7867                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in orr()
7909     Register rm = operand.GetBaseRegister();  in orrs()  local
7912         // ORRS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in orrs()
7914             rm.IsLow()) {  in orrs()
7915           EmitT32_16(0x4300 | rd.GetCode() | (rm.GetCode() << 3));  in orrs()
7924       // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in orrs()
7926           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in orrs()
7929                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in orrs()
7935       // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in orrs()
7939                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in orrs()
7946     Register rm = operand.GetBaseRegister();  in orrs()  local
7950       // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in orrs()
7952           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in orrs()
7955                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in orrs()
7971     Register rm = operand.GetBaseRegister();  in pkhbt()  local
7975       // PKHBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, LSL #<imm> } ; T1  in pkhbt()
7977           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in pkhbt()
7979                    rm.GetCode() | ((amount & 0x3) << 6) |  in pkhbt()
7985       // PKHBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, LSL #<imm> } ; A1  in pkhbt()
7987           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in pkhbt()
7989                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in pkhbt()
8005     Register rm = operand.GetBaseRegister();  in pkhtb()  local
8009       // PKHTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ASR #<imm> } ; T1  in pkhtb()
8011           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in pkhtb()
8014                    rm.GetCode() | ((amount_ & 0x3) << 6) |  in pkhtb()
8020       // PKHTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ASR #<imm> } ; A1  in pkhtb()
8023           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in pkhtb()
8026                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in pkhtb()
8179     Register rm = operand.GetOffsetRegister();  in pld()  local
8183       // PLD{<c>}{<q>} [<Rn>, {+}<Rm>{, LSL #<amount>}] ; T1  in pld()
8186           (!rm.IsPC() || AllowUnpredictable())) {  in pld()
8187         EmitT32_32(0xf810f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pld()
8193       // PLD{<c>}{<q>} [<Rn>, {+/-}<Rm>{, <shift> #<amount_1>}] ; A1  in pld()
8195           (!rm.IsPC() || AllowUnpredictable())) {  in pld()
8199           EmitA32(0xf750f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pld()
8204       // PLD{<c>}{<q>} [<Rn>, {+/-}<Rm>, RRX] ; A1  in pld()
8206           (!rm.IsPC() || AllowUnpredictable())) {  in pld()
8209           EmitA32(0xf750f060U | (rn.GetCode() << 16) | rm.GetCode() |  in pld()
8256     Register rm = operand.GetOffsetRegister();  in pldw()  local
8260       // PLDW{<c>}{<q>} [<Rn>, {+}<Rm>{, LSL #<amount>}] ; T1  in pldw()
8263           (!rm.IsPC() || AllowUnpredictable())) {  in pldw()
8264         EmitT32_32(0xf830f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pldw()
8270       // PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm>{, <shift> #<amount_1>}] ; A1  in pldw()
8272           (!rm.IsPC() || AllowUnpredictable())) {  in pldw()
8276           EmitA32(0xf710f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pldw()
8281       // PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm>, RRX] ; A1  in pldw()
8283           (!rm.IsPC() || AllowUnpredictable())) {  in pldw()
8286           EmitA32(0xf710f060U | (rn.GetCode() << 16) | rm.GetCode() |  in pldw()
8359     Register rm = operand.GetOffsetRegister();  in pli()  local
8363       // PLI{<c>}{<q>} [<Rn>, {+}<Rm>{, LSL #<amount>}] ; T1  in pli()
8366           (!rm.IsPC() || AllowUnpredictable())) {  in pli()
8367         EmitT32_32(0xf910f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pli()
8373       // PLI{<c>}{<q>} [<Rn>, {+/-}<Rm>, RRX] ; A1  in pli()
8375           (!rm.IsPC() || AllowUnpredictable())) {  in pli()
8378           EmitA32(0xf650f060U | (rn.GetCode() << 16) | rm.GetCode() |  in pli()
8383       // PLI{<c>}{<q>} [<Rn>, {+/-}<Rm>{, <shift> #<amount_1>}] ; A1  in pli()
8385           (!rm.IsPC() || AllowUnpredictable())) {  in pli()
8389           EmitA32(0xf650f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pli()
8611 void Assembler::qadd(Condition cond, Register rd, Register rm, Register rn) {  in qadd()  argument
8615     // QADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1  in qadd()
8616     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd()
8617       EmitT32_32(0xfa80f080U | (rd.GetCode() << 8) | rm.GetCode() |  in qadd()
8623     // QADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1  in qadd()
8625         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd()
8627               rm.GetCode() | (rn.GetCode() << 16));  in qadd()
8631   Delegate(kQadd, &Assembler::qadd, cond, rd, rm, rn);  in qadd()
8634 void Assembler::qadd16(Condition cond, Register rd, Register rn, Register rm) {  in qadd16()  argument
8638     // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in qadd16()
8639     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd16()
8641                  rm.GetCode());  in qadd16()
8646     // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in qadd16()
8648         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd16()
8650               (rn.GetCode() << 16) | rm.GetCode());  in qadd16()
8654   Delegate(kQadd16, &Assembler::qadd16, cond, rd, rn, rm);  in qadd16()
8657 void Assembler::qadd8(Condition cond, Register rd, Register rn, Register rm) {  in qadd8()  argument
8661     // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in qadd8()
8662     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd8()
8664                  rm.GetCode());  in qadd8()
8669     // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in qadd8()
8671         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd8()
8673               (rn.GetCode() << 16) | rm.GetCode());  in qadd8()
8677   Delegate(kQadd8, &Assembler::qadd8, cond, rd, rn, rm);  in qadd8()
8680 void Assembler::qasx(Condition cond, Register rd, Register rn, Register rm) {  in qasx()  argument
8684     // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in qasx()
8685     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qasx()
8687                  rm.GetCode());  in qasx()
8692     // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in qasx()
8694         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qasx()
8696               (rn.GetCode() << 16) | rm.GetCode());  in qasx()
8700   Delegate(kQasx, &Assembler::qasx, cond, rd, rn, rm);  in qasx()
8703 void Assembler::qdadd(Condition cond, Register rd, Register rm, Register rn) {  in qdadd()  argument
8707     // QDADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1  in qdadd()
8708     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qdadd()
8709       EmitT32_32(0xfa80f090U | (rd.GetCode() << 8) | rm.GetCode() |  in qdadd()
8715     // QDADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1  in qdadd()
8717         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qdadd()
8719               rm.GetCode() | (rn.GetCode() << 16));  in qdadd()
8723   Delegate(kQdadd, &Assembler::qdadd, cond, rd, rm, rn);  in qdadd()
8726 void Assembler::qdsub(Condition cond, Register rd, Register rm, Register rn) {  in qdsub()  argument
8730     // QDSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1  in qdsub()
8731     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qdsub()
8732       EmitT32_32(0xfa80f0b0U | (rd.GetCode() << 8) | rm.GetCode() |  in qdsub()
8738     // QDSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1  in qdsub()
8740         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qdsub()
8742               rm.GetCode() | (rn.GetCode() << 16));  in qdsub()
8746   Delegate(kQdsub, &Assembler::qdsub, cond, rd, rm, rn);  in qdsub()
8749 void Assembler::qsax(Condition cond, Register rd, Register rn, Register rm) {  in qsax()  argument
8753     // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in qsax()
8754     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsax()
8756                  rm.GetCode());  in qsax()
8761     // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in qsax()
8763         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsax()
8765               (rn.GetCode() << 16) | rm.GetCode());  in qsax()
8769   Delegate(kQsax, &Assembler::qsax, cond, rd, rn, rm);  in qsax()
8772 void Assembler::qsub(Condition cond, Register rd, Register rm, Register rn) {  in qsub()  argument
8776     // QSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1  in qsub()
8777     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub()
8778       EmitT32_32(0xfa80f0a0U | (rd.GetCode() << 8) | rm.GetCode() |  in qsub()
8784     // QSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1  in qsub()
8786         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub()
8788               rm.GetCode() | (rn.GetCode() << 16));  in qsub()
8792   Delegate(kQsub, &Assembler::qsub, cond, rd, rm, rn);  in qsub()
8795 void Assembler::qsub16(Condition cond, Register rd, Register rn, Register rm) {  in qsub16()  argument
8799     // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in qsub16()
8800     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub16()
8802                  rm.GetCode());  in qsub16()
8807     // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in qsub16()
8809         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub16()
8811               (rn.GetCode() << 16) | rm.GetCode());  in qsub16()
8815   Delegate(kQsub16, &Assembler::qsub16, cond, rd, rn, rm);  in qsub16()
8818 void Assembler::qsub8(Condition cond, Register rd, Register rn, Register rm) {  in qsub8()  argument
8822     // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in qsub8()
8823     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub8()
8825                  rm.GetCode());  in qsub8()
8830     // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in qsub8()
8832         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub8()
8834               (rn.GetCode() << 16) | rm.GetCode());  in qsub8()
8838   Delegate(kQsub8, &Assembler::qsub8, cond, rd, rn, rm);  in qsub8()
8841 void Assembler::rbit(Condition cond, Register rd, Register rm) {  in rbit()  argument
8845     // RBIT{<c>}{<q>} <Rd>, <Rm> ; T1  in rbit()
8846     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rbit()
8847       EmitT32_32(0xfa90f0a0U | (rd.GetCode() << 8) | rm.GetCode() |  in rbit()
8848                  (rm.GetCode() << 16));  in rbit()
8853     // RBIT{<c>}{<q>} <Rd>, <Rm> ; A1  in rbit()
8855         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rbit()
8857               rm.GetCode());  in rbit()
8861   Delegate(kRbit, &Assembler::rbit, cond, rd, rm);  in rbit()
8867                     Register rm) {  in rev()  argument
8871     // REV{<c>}{<q>} <Rd>, <Rm> ; T1  in rev()
8872     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in rev()
8873       EmitT32_16(0xba00 | rd.GetCode() | (rm.GetCode() << 3));  in rev()
8877     // REV{<c>}{<q>} <Rd>, <Rm> ; T2  in rev()
8879         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rev()
8880       EmitT32_32(0xfa90f080U | (rd.GetCode() << 8) | rm.GetCode() |  in rev()
8881                  (rm.GetCode() << 16));  in rev()
8886     // REV{<c>}{<q>} <Rd>, <Rm> ; A1  in rev()
8888         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rev()
8890               rm.GetCode());  in rev()
8894   Delegate(kRev, &Assembler::rev, cond, size, rd, rm);  in rev()
8900                       Register rm) {  in rev16()  argument
8904     // REV16{<c>}{<q>} <Rd>, <Rm> ; T1  in rev16()
8905     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in rev16()
8906       EmitT32_16(0xba40 | rd.GetCode() | (rm.GetCode() << 3));  in rev16()
8910     // REV16{<c>}{<q>} <Rd>, <Rm> ; T2  in rev16()
8912         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rev16()
8913       EmitT32_32(0xfa90f090U | (rd.GetCode() << 8) | rm.GetCode() |  in rev16()
8914                  (rm.GetCode() << 16));  in rev16()
8919     // REV16{<c>}{<q>} <Rd>, <Rm> ; A1  in rev16()
8921         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rev16()
8923               rm.GetCode());  in rev16()
8927   Delegate(kRev16, &Assembler::rev16, cond, size, rd, rm);  in rev16()
8933                       Register rm) {  in revsh()  argument
8937     // REVSH{<c>}{<q>} <Rd>, <Rm> ; T1  in revsh()
8938     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in revsh()
8939       EmitT32_16(0xbac0 | rd.GetCode() | (rm.GetCode() << 3));  in revsh()
8943     // REVSH{<c>}{<q>} <Rd>, <Rm> ; T2  in revsh()
8945         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in revsh()
8946       EmitT32_32(0xfa90f0b0U | (rd.GetCode() << 8) | rm.GetCode() |  in revsh()
8947                  (rm.GetCode() << 16));  in revsh()
8952     // REVSH{<c>}{<q>} <Rd>, <Rm> ; A1  in revsh()
8954         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in revsh()
8956               rm.GetCode());  in revsh()
8960   Delegate(kRevsh, &Assembler::revsh, cond, size, rd, rm);  in revsh()
8966                     Register rm,  in ror()  argument
8973       // ROR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3  in ror()
8975           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ror()
8976         EmitT32_32(0xea4f0030U | (rd.GetCode() << 8) | rm.GetCode() |  in ror()
8982       // ROR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1  in ror()
8985                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));  in ror()
8994       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in ror()
9000       // ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2  in ror()
9002           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in ror()
9003         EmitT32_32(0xfa60f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in ror()
9009       // ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1  in ror()
9011           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in ror()
9013                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in ror()
9018   Delegate(kRor, &Assembler::ror, cond, size, rd, rm, operand);  in ror()
9024                      Register rm,  in rors()  argument
9031       // RORS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3  in rors()
9033           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rors()
9034         EmitT32_32(0xea5f0030U | (rd.GetCode() << 8) | rm.GetCode() |  in rors()
9040       // RORS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1  in rors()
9043                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));  in rors()
9052       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in rors()
9058       // RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2  in rors()
9060           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in rors()
9061         EmitT32_32(0xfa70f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in rors()
9067       // RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1  in rors()
9069           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in rors()
9071                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in rors()
9076   Delegate(kRors, &Assembler::rors, cond, size, rd, rm, operand);  in rors()
9079 void Assembler::rrx(Condition cond, Register rd, Register rm) {  in rrx()  argument
9083     // RRX{<c>}{<q>} {<Rd>}, <Rm> ; T3  in rrx()
9084     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rrx()
9085       EmitT32_32(0xea4f0030U | (rd.GetCode() << 8) | rm.GetCode());  in rrx()
9090     // RRX{<c>}{<q>} {<Rd>}, <Rm> ; A1  in rrx()
9093               rm.GetCode());  in rrx()
9097   Delegate(kRrx, &Assembler::rrx, cond, rd, rm);  in rrx()
9100 void Assembler::rrxs(Condition cond, Register rd, Register rm) {  in rrxs()  argument
9104     // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; T3  in rrxs()
9105     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rrxs()
9106       EmitT32_32(0xea5f0030U | (rd.GetCode() << 8) | rm.GetCode());  in rrxs()
9111     // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; A1  in rrxs()
9114               rm.GetCode());  in rrxs()
9118   Delegate(kRrxs, &Assembler::rrxs, cond, rd, rm);  in rrxs()
9161     Register rm = operand.GetBaseRegister();  in rsb()  local
9165       // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1  in rsb()
9167           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rsb()
9170                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in rsb()
9176       // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in rsb()
9180                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsb()
9187     Register rm = operand.GetBaseRegister();  in rsb()  local
9191       // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in rsb()
9193           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in rsb()
9196                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsb()
9245     Register rm = operand.GetBaseRegister();  in rsbs()  local
9249       // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1  in rsbs()
9251           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rsbs()
9254                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in rsbs()
9260       // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in rsbs()
9264                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsbs()
9271     Register rm = operand.GetBaseRegister();  in rsbs()  local
9275       // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in rsbs()
9277           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in rsbs()
9280                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsbs()
9309     Register rm = operand.GetBaseRegister();  in rsc()  local
9313       // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in rsc()
9317                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsc()
9324     Register rm = operand.GetBaseRegister();  in rsc()  local
9328       // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in rsc()
9330           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in rsc()
9333                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsc()
9362     Register rm = operand.GetBaseRegister();  in rscs()  local
9366       // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in rscs()
9370                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rscs()
9377     Register rm = operand.GetBaseRegister();  in rscs()  local
9381       // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in rscs()
9383           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in rscs()
9386                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rscs()
9395 void Assembler::sadd16(Condition cond, Register rd, Register rn, Register rm) {  in sadd16()  argument
9399     // SADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in sadd16()
9400     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sadd16()
9402                  rm.GetCode());  in sadd16()
9407     // SADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in sadd16()
9409         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sadd16()
9411               (rn.GetCode() << 16) | rm.GetCode());  in sadd16()
9415   Delegate(kSadd16, &Assembler::sadd16, cond, rd, rn, rm);  in sadd16()
9418 void Assembler::sadd8(Condition cond, Register rd, Register rn, Register rm) {  in sadd8()  argument
9422     // SADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in sadd8()
9423     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sadd8()
9425                  rm.GetCode());  in sadd8()
9430     // SADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in sadd8()
9432         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sadd8()
9434               (rn.GetCode() << 16) | rm.GetCode());  in sadd8()
9438   Delegate(kSadd8, &Assembler::sadd8, cond, rd, rn, rm);  in sadd8()
9441 void Assembler::sasx(Condition cond, Register rd, Register rn, Register rm) {  in sasx()  argument
9445     // SASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in sasx()
9446     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sasx()
9448                  rm.GetCode());  in sasx()
9453     // SASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in sasx()
9455         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sasx()
9457               (rn.GetCode() << 16) | rm.GetCode());  in sasx()
9461   Delegate(kSasx, &Assembler::sasx, cond, rd, rn, rm);  in sasx()
9497     Register rm = operand.GetBaseRegister();  in sbc()  local
9500         // SBC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in sbc()
9502             rm.IsLow()) {  in sbc()
9503           EmitT32_16(0x4180 | rd.GetCode() | (rm.GetCode() << 3));  in sbc()
9512       // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in sbc()
9514           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sbc()
9517                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in sbc()
9523       // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in sbc()
9527                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sbc()
9534     Register rm = operand.GetBaseRegister();  in sbc()  local
9538       // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in sbc()
9540           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in sbc()
9543                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sbc()
9585     Register rm = operand.GetBaseRegister();  in sbcs()  local
9588         // SBCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1  in sbcs()
9590             rm.IsLow()) {  in sbcs()
9591           EmitT32_16(0x4180 | rd.GetCode() | (rm.GetCode() << 3));  in sbcs()
9600       // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in sbcs()
9602           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sbcs()
9605                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in sbcs()
9611       // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in sbcs()
9615                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sbcs()
9622     Register rm = operand.GetBaseRegister();  in sbcs()  local
9626       // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in sbcs()
9628           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in sbcs()
9631                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sbcs()
9669 void Assembler::sdiv(Condition cond, Register rd, Register rn, Register rm) {  in sdiv()  argument
9673     // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in sdiv()
9674     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sdiv()
9676                  rm.GetCode());  in sdiv()
9681     // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in sdiv()
9683         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sdiv()
9685               rn.GetCode() | (rm.GetCode() << 8));  in sdiv()
9689   Delegate(kSdiv, &Assembler::sdiv, cond, rd, rn, rm);  in sdiv()
9692 void Assembler::sel(Condition cond, Register rd, Register rn, Register rm) {  in sel()  argument
9696     // SEL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in sel()
9697     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sel()
9699                  rm.GetCode());  in sel()
9704     // SEL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in sel()
9706         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sel()
9708               (rn.GetCode() << 16) | rm.GetCode());  in sel()
9712   Delegate(kSel, &Assembler::sel, cond, rd, rn, rm);  in sel()
9715 void Assembler::shadd16(Condition cond, Register rd, Register rn, Register rm) {  in shadd16()  argument
9719     // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in shadd16()
9720     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shadd16()
9722                  rm.GetCode());  in shadd16()
9727     // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in shadd16()
9729         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shadd16()
9731               (rn.GetCode() << 16) | rm.GetCode());  in shadd16()
9735   Delegate(kShadd16, &Assembler::shadd16, cond, rd, rn, rm);  in shadd16()
9738 void Assembler::shadd8(Condition cond, Register rd, Register rn, Register rm) {  in shadd8()  argument
9742     // SHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in shadd8()
9743     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shadd8()
9745                  rm.GetCode());  in shadd8()
9750     // SHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in shadd8()
9752         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shadd8()
9754               (rn.GetCode() << 16) | rm.GetCode());  in shadd8()
9758   Delegate(kShadd8, &Assembler::shadd8, cond, rd, rn, rm);  in shadd8()
9761 void Assembler::shasx(Condition cond, Register rd, Register rn, Register rm) {  in shasx()  argument
9765     // SHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in shasx()
9766     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shasx()
9768                  rm.GetCode());  in shasx()
9773     // SHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in shasx()
9775         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shasx()
9777               (rn.GetCode() << 16) | rm.GetCode());  in shasx()
9781   Delegate(kShasx, &Assembler::shasx, cond, rd, rn, rm);  in shasx()
9784 void Assembler::shsax(Condition cond, Register rd, Register rn, Register rm) {  in shsax()  argument
9788     // SHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in shsax()
9789     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsax()
9791                  rm.GetCode());  in shsax()
9796     // SHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in shsax()
9798         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsax()
9800               (rn.GetCode() << 16) | rm.GetCode());  in shsax()
9804   Delegate(kShsax, &Assembler::shsax, cond, rd, rn, rm);  in shsax()
9807 void Assembler::shsub16(Condition cond, Register rd, Register rn, Register rm) {  in shsub16()  argument
9811     // SHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in shsub16()
9812     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsub16()
9814                  rm.GetCode());  in shsub16()
9819     // SHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in shsub16()
9821         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsub16()
9823               (rn.GetCode() << 16) | rm.GetCode());  in shsub16()
9827   Delegate(kShsub16, &Assembler::shsub16, cond, rd, rn, rm);  in shsub16()
9830 void Assembler::shsub8(Condition cond, Register rd, Register rn, Register rm) {  in shsub8()  argument
9834     // SHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in shsub8()
9835     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsub8()
9837                  rm.GetCode());  in shsub8()
9842     // SHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in shsub8()
9844         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsub8()
9846               (rn.GetCode() << 16) | rm.GetCode());  in shsub8()
9850   Delegate(kShsub8, &Assembler::shsub8, cond, rd, rn, rm);  in shsub8()
9854     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlabb()  argument
9858     // SMLABB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlabb()
9860         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlabb()
9862                  rm.GetCode() | (ra.GetCode() << 12));  in smlabb()
9867     // SMLABB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlabb()
9869         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlabb()
9872               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlabb()
9876   Delegate(kSmlabb, &Assembler::smlabb, cond, rd, rn, rm, ra);  in smlabb()
9880     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlabt()  argument
9884     // SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlabt()
9886         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlabt()
9888                  rm.GetCode() | (ra.GetCode() << 12));  in smlabt()
9893     // SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlabt()
9895         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlabt()
9898               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlabt()
9902   Delegate(kSmlabt, &Assembler::smlabt, cond, rd, rn, rm, ra);  in smlabt()
9906     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlad()  argument
9910     // SMLAD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlad()
9912         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlad()
9914                  rm.GetCode() | (ra.GetCode() << 12));  in smlad()
9919     // SMLAD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlad()
9921         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlad()
9923               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlad()
9927   Delegate(kSmlad, &Assembler::smlad, cond, rd, rn, rm, ra);  in smlad()
9931     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smladx()  argument
9935     // SMLADX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smladx()
9937         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smladx()
9939                  rm.GetCode() | (ra.GetCode() << 12));  in smladx()
9944     // SMLADX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smladx()
9946         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smladx()
9948               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smladx()
9952   Delegate(kSmladx, &Assembler::smladx, cond, rd, rn, rm, ra);  in smladx()
9956     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlal()  argument
9960     // SMLAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlal()
9961     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlal()
9964                  (rn.GetCode() << 16) | rm.GetCode());  in smlal()
9969     // SMLAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlal()
9971         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlal()
9975               (rm.GetCode() << 8));  in smlal()
9979   Delegate(kSmlal, &Assembler::smlal, cond, rdlo, rdhi, rn, rm);  in smlal()
9983     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlalbb()  argument
9987     // SMLALBB{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlalbb()
9988     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlalbb()
9991                  (rn.GetCode() << 16) | rm.GetCode());  in smlalbb()
9996     // SMLALBB{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlalbb()
9998         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlalbb()
10002               (rm.GetCode() << 8));  in smlalbb()
10006   Delegate(kSmlalbb, &Assembler::smlalbb, cond, rdlo, rdhi, rn, rm);  in smlalbb()
10010     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlalbt()  argument
10014     // SMLALBT{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlalbt()
10015     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlalbt()
10018                  (rn.GetCode() << 16) | rm.GetCode());  in smlalbt()
10023     // SMLALBT{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlalbt()
10025         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlalbt()
10029               (rm.GetCode() << 8));  in smlalbt()
10033   Delegate(kSmlalbt, &Assembler::smlalbt, cond, rdlo, rdhi, rn, rm);  in smlalbt()
10037     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlald()  argument
10041     // SMLALD{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlald()
10042     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlald()
10045                  (rn.GetCode() << 16) | rm.GetCode());  in smlald()
10050     // SMLALD{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlald()
10052         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlald()
10056               (rm.GetCode() << 8));  in smlald()
10060   Delegate(kSmlald, &Assembler::smlald, cond, rdlo, rdhi, rn, rm);  in smlald()
10064     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlaldx()  argument
10068     // SMLALDX{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlaldx()
10069     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaldx()
10072                  (rn.GetCode() << 16) | rm.GetCode());  in smlaldx()
10077     // SMLALDX{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlaldx()
10079         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaldx()
10083               (rm.GetCode() << 8));  in smlaldx()
10087   Delegate(kSmlaldx, &Assembler::smlaldx, cond, rdlo, rdhi, rn, rm);  in smlaldx()
10091     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlals()  argument
10095     // SMLALS{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlals()
10097         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlals()
10101               (rm.GetCode() << 8));  in smlals()
10105   Delegate(kSmlals, &Assembler::smlals, cond, rdlo, rdhi, rn, rm);  in smlals()
10109     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlaltb()  argument
10113     // SMLALTB{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlaltb()
10114     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaltb()
10117                  (rn.GetCode() << 16) | rm.GetCode());  in smlaltb()
10122     // SMLALTB{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlaltb()
10124         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaltb()
10128               (rm.GetCode() << 8));  in smlaltb()
10132   Delegate(kSmlaltb, &Assembler::smlaltb, cond, rdlo, rdhi, rn, rm);  in smlaltb()
10136     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlaltt()  argument
10140     // SMLALTT{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlaltt()
10141     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaltt()
10144                  (rn.GetCode() << 16) | rm.GetCode());  in smlaltt()
10149     // SMLALTT{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlaltt()
10151         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaltt()
10155               (rm.GetCode() << 8));  in smlaltt()
10159   Delegate(kSmlaltt, &Assembler::smlaltt, cond, rdlo, rdhi, rn, rm);  in smlaltt()
10163     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlatb()  argument
10167     // SMLATB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlatb()
10169         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlatb()
10171                  rm.GetCode() | (ra.GetCode() << 12));  in smlatb()
10176     // SMLATB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlatb()
10178         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlatb()
10181               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlatb()
10185   Delegate(kSmlatb, &Assembler::smlatb, cond, rd, rn, rm, ra);  in smlatb()
10189     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlatt()  argument
10193     // SMLATT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlatt()
10195         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlatt()
10197                  rm.GetCode() | (ra.GetCode() << 12));  in smlatt()
10202     // SMLATT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlatt()
10204         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlatt()
10207               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlatt()
10211   Delegate(kSmlatt, &Assembler::smlatt, cond, rd, rn, rm, ra);  in smlatt()
10215     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlawb()  argument
10219     // SMLAWB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlawb()
10221         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlawb()
10223                  rm.GetCode() | (ra.GetCode() << 12));  in smlawb()
10228     // SMLAWB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlawb()
10230         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlawb()
10233               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlawb()
10237   Delegate(kSmlawb, &Assembler::smlawb, cond, rd, rn, rm, ra);  in smlawb()
10241     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlawt()  argument
10245     // SMLAWT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlawt()
10247         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlawt()
10249                  rm.GetCode() | (ra.GetCode() << 12));  in smlawt()
10254     // SMLAWT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlawt()
10256         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlawt()
10259               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlawt()
10263   Delegate(kSmlawt, &Assembler::smlawt, cond, rd, rn, rm, ra);  in smlawt()
10267     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlsd()  argument
10271     // SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlsd()
10273         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlsd()
10275                  rm.GetCode() | (ra.GetCode() << 12));  in smlsd()
10280     // SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlsd()
10282         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlsd()
10284               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlsd()
10288   Delegate(kSmlsd, &Assembler::smlsd, cond, rd, rn, rm, ra);  in smlsd()
10292     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlsdx()  argument
10296     // SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smlsdx()
10298         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlsdx()
10300                  rm.GetCode() | (ra.GetCode() << 12));  in smlsdx()
10305     // SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smlsdx()
10307         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlsdx()
10309               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlsdx()
10313   Delegate(kSmlsdx, &Assembler::smlsdx, cond, rd, rn, rm, ra);  in smlsdx()
10317     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlsld()  argument
10321     // SMLSLD{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlsld()
10322     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlsld()
10325                  (rn.GetCode() << 16) | rm.GetCode());  in smlsld()
10330     // SMLSLD{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlsld()
10332         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlsld()
10336               (rm.GetCode() << 8));  in smlsld()
10340   Delegate(kSmlsld, &Assembler::smlsld, cond, rdlo, rdhi, rn, rm);  in smlsld()
10344     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlsldx()  argument
10348     // SMLSLDX{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smlsldx()
10349     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlsldx()
10352                  (rn.GetCode() << 16) | rm.GetCode());  in smlsldx()
10357     // SMLSLDX{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smlsldx()
10359         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlsldx()
10363               (rm.GetCode() << 8));  in smlsldx()
10367   Delegate(kSmlsldx, &Assembler::smlsldx, cond, rdlo, rdhi, rn, rm);  in smlsldx()
10371     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smmla()  argument
10375     // SMMLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smmla()
10377         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmla()
10379                  rm.GetCode() | (ra.GetCode() << 12));  in smmla()
10384     // SMMLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smmla()
10386         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmla()
10388               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smmla()
10392   Delegate(kSmmla, &Assembler::smmla, cond, rd, rn, rm, ra);  in smmla()
10396     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smmlar()  argument
10400     // SMMLAR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smmlar()
10402         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmlar()
10404                  rm.GetCode() | (ra.GetCode() << 12));  in smmlar()
10409     // SMMLAR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smmlar()
10411         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmlar()
10413               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smmlar()
10417   Delegate(kSmmlar, &Assembler::smmlar, cond, rd, rn, rm, ra);  in smmlar()
10421     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smmls()  argument
10425     // SMMLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smmls()
10426     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smmls()
10429                  rm.GetCode() | (ra.GetCode() << 12));  in smmls()
10434     // SMMLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smmls()
10436         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smmls()
10439               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smmls()
10443   Delegate(kSmmls, &Assembler::smmls, cond, rd, rn, rm, ra);  in smmls()
10447     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smmlsr()  argument
10451     // SMMLSR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in smmlsr()
10452     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smmlsr()
10455                  rm.GetCode() | (ra.GetCode() << 12));  in smmlsr()
10460     // SMMLSR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in smmlsr()
10462         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smmlsr()
10465               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smmlsr()
10469   Delegate(kSmmlsr, &Assembler::smmlsr, cond, rd, rn, rm, ra);  in smmlsr()
10472 void Assembler::smmul(Condition cond, Register rd, Register rn, Register rm) {  in smmul()  argument
10476     // SMMUL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smmul()
10477     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmul()
10479                  rm.GetCode());  in smmul()
10484     // SMMUL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smmul()
10486         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmul()
10488               rn.GetCode() | (rm.GetCode() << 8));  in smmul()
10492   Delegate(kSmmul, &Assembler::smmul, cond, rd, rn, rm);  in smmul()
10495 void Assembler::smmulr(Condition cond, Register rd, Register rn, Register rm) {  in smmulr()  argument
10499     // SMMULR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smmulr()
10500     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmulr()
10502                  rm.GetCode());  in smmulr()
10507     // SMMULR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smmulr()
10509         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmulr()
10511               rn.GetCode() | (rm.GetCode() << 8));  in smmulr()
10515   Delegate(kSmmulr, &Assembler::smmulr, cond, rd, rn, rm);  in smmulr()
10518 void Assembler::smuad(Condition cond, Register rd, Register rn, Register rm) {  in smuad()  argument
10522     // SMUAD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smuad()
10523     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smuad()
10525                  rm.GetCode());  in smuad()
10530     // SMUAD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smuad()
10532         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smuad()
10534               rn.GetCode() | (rm.GetCode() << 8));  in smuad()
10538   Delegate(kSmuad, &Assembler::smuad, cond, rd, rn, rm);  in smuad()
10541 void Assembler::smuadx(Condition cond, Register rd, Register rn, Register rm) {  in smuadx()  argument
10545     // SMUADX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smuadx()
10546     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smuadx()
10548                  rm.GetCode());  in smuadx()
10553     // SMUADX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smuadx()
10555         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smuadx()
10557               rn.GetCode() | (rm.GetCode() << 8));  in smuadx()
10561   Delegate(kSmuadx, &Assembler::smuadx, cond, rd, rn, rm);  in smuadx()
10564 void Assembler::smulbb(Condition cond, Register rd, Register rn, Register rm) {  in smulbb()  argument
10568     // SMULBB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smulbb()
10569     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulbb()
10571                  rm.GetCode());  in smulbb()
10576     // SMULBB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smulbb()
10578         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulbb()
10580               rn.GetCode() | (rm.GetCode() << 8));  in smulbb()
10584   Delegate(kSmulbb, &Assembler::smulbb, cond, rd, rn, rm);  in smulbb()
10587 void Assembler::smulbt(Condition cond, Register rd, Register rn, Register rm) {  in smulbt()  argument
10591     // SMULBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smulbt()
10592     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulbt()
10594                  rm.GetCode());  in smulbt()
10599     // SMULBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smulbt()
10601         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulbt()
10603               rn.GetCode() | (rm.GetCode() << 8));  in smulbt()
10607   Delegate(kSmulbt, &Assembler::smulbt, cond, rd, rn, rm);  in smulbt()
10611     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smull()  argument
10615     // SMULL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in smull()
10616     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smull()
10619                  (rn.GetCode() << 16) | rm.GetCode());  in smull()
10624     // SMULL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smull()
10626         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smull()
10630               (rm.GetCode() << 8));  in smull()
10634   Delegate(kSmull, &Assembler::smull, cond, rdlo, rdhi, rn, rm);  in smull()
10638     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smulls()  argument
10642     // SMULLS{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in smulls()
10644         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smulls()
10648               (rm.GetCode() << 8));  in smulls()
10652   Delegate(kSmulls, &Assembler::smulls, cond, rdlo, rdhi, rn, rm);  in smulls()
10655 void Assembler::smultb(Condition cond, Register rd, Register rn, Register rm) {  in smultb()  argument
10659     // SMULTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smultb()
10660     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smultb()
10662                  rm.GetCode());  in smultb()
10667     // SMULTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smultb()
10669         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smultb()
10671               rn.GetCode() | (rm.GetCode() << 8));  in smultb()
10675   Delegate(kSmultb, &Assembler::smultb, cond, rd, rn, rm);  in smultb()
10678 void Assembler::smultt(Condition cond, Register rd, Register rn, Register rm) {  in smultt()  argument
10682     // SMULTT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smultt()
10683     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smultt()
10685                  rm.GetCode());  in smultt()
10690     // SMULTT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smultt()
10692         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smultt()
10694               rn.GetCode() | (rm.GetCode() << 8));  in smultt()
10698   Delegate(kSmultt, &Assembler::smultt, cond, rd, rn, rm);  in smultt()
10701 void Assembler::smulwb(Condition cond, Register rd, Register rn, Register rm) {  in smulwb()  argument
10705     // SMULWB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smulwb()
10706     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulwb()
10708                  rm.GetCode());  in smulwb()
10713     // SMULWB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smulwb()
10715         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulwb()
10717               rn.GetCode() | (rm.GetCode() << 8));  in smulwb()
10721   Delegate(kSmulwb, &Assembler::smulwb, cond, rd, rn, rm);  in smulwb()
10724 void Assembler::smulwt(Condition cond, Register rd, Register rn, Register rm) {  in smulwt()  argument
10728     // SMULWT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smulwt()
10729     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulwt()
10731                  rm.GetCode());  in smulwt()
10736     // SMULWT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smulwt()
10738         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulwt()
10740               rn.GetCode() | (rm.GetCode() << 8));  in smulwt()
10744   Delegate(kSmulwt, &Assembler::smulwt, cond, rd, rn, rm);  in smulwt()
10747 void Assembler::smusd(Condition cond, Register rd, Register rn, Register rm) {  in smusd()  argument
10751     // SMUSD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smusd()
10752     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smusd()
10754                  rm.GetCode());  in smusd()
10759     // SMUSD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smusd()
10761         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smusd()
10763               rn.GetCode() | (rm.GetCode() << 8));  in smusd()
10767   Delegate(kSmusd, &Assembler::smusd, cond, rd, rn, rm);  in smusd()
10770 void Assembler::smusdx(Condition cond, Register rd, Register rn, Register rm) {  in smusdx()  argument
10774     // SMUSDX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in smusdx()
10775     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smusdx()
10777                  rm.GetCode());  in smusdx()
10782     // SMUSDX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in smusdx()
10784         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smusdx()
10786               rn.GetCode() | (rm.GetCode() << 8));  in smusdx()
10790   Delegate(kSmusdx, &Assembler::smusdx, cond, rd, rn, rm);  in smusdx()
10878 void Assembler::ssax(Condition cond, Register rd, Register rn, Register rm) {  in ssax()  argument
10882     // SSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in ssax()
10883     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssax()
10885                  rm.GetCode());  in ssax()
10890     // SSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in ssax()
10892         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssax()
10894               (rn.GetCode() << 16) | rm.GetCode());  in ssax()
10898   Delegate(kSsax, &Assembler::ssax, cond, rd, rn, rm);  in ssax()
10901 void Assembler::ssub16(Condition cond, Register rd, Register rn, Register rm) {  in ssub16()  argument
10905     // SSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in ssub16()
10906     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssub16()
10908                  rm.GetCode());  in ssub16()
10913     // SSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in ssub16()
10915         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssub16()
10917               (rn.GetCode() << 16) | rm.GetCode());  in ssub16()
10921   Delegate(kSsub16, &Assembler::ssub16, cond, rd, rn, rm);  in ssub16()
10924 void Assembler::ssub8(Condition cond, Register rd, Register rn, Register rm) {  in ssub8()  argument
10928     // SSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in ssub8()
10929     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssub8()
10931                  rm.GetCode());  in ssub8()
10936     // SSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in ssub8()
10938         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssub8()
10940               (rn.GetCode() << 16) | rm.GetCode());  in ssub8()
10944   Delegate(kSsub8, &Assembler::ssub8, cond, rd, rn, rm);  in ssub8()
11478     Register rm = operand.GetOffsetRegister();  in str()  local
11480       // STR{<c>}{<q>} <Rt>, [<Rn>, #{+}<Rm>] ; T1  in str()
11481       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in str()
11484                    (rm.GetCode() << 6));  in str()
11493     Register rm = operand.GetOffsetRegister();  in str()  local
11497       // STR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}] ; T2  in str()
11500           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in str()
11502                    rm.GetCode() | (amount << 4));  in str()
11507       // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1  in str()
11509           (!rm.IsPC() || AllowUnpredictable())) {  in str()
11514                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in str()
11518       // STR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1  in str()
11520           cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {  in str()
11525                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in str()
11529       // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1  in str()
11531           (!rm.IsPC() || AllowUnpredictable())) {  in str()
11536                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in str()
11639     Register rm = operand.GetOffsetRegister();  in strb()  local
11641       // STRB{<c>}{<q>} <Rt>, [<Rn>, #{+}<Rm>] ; T1  in strb()
11642       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in strb()
11645                    (rm.GetCode() << 6));  in strb()
11654     Register rm = operand.GetOffsetRegister();  in strb()  local
11658       // STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}] ; T2  in strb()
11661           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strb()
11663                    rm.GetCode() | (amount << 4));  in strb()
11668       // STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1  in strb()
11670           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strb()
11675                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strb()
11679       // STRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1  in strb()
11682           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strb()
11687                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strb()
11691       // STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1  in strb()
11693           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strb()
11698                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strb()
11792     Register rm = operand.GetOffsetRegister();  in strd()  local
11794       // STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<Rm>] ; A1  in strd()
11797           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in strd()
11801                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strd()
11805       // STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<Rm> ; A1  in strd()
11808           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in strd()
11812                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strd()
11816       // STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<Rm>]! ; A1  in strd()
11819           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in strd()
11823                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strd()
12055     Register rm = operand.GetOffsetRegister();  in strh()  local
12057       // STRH{<c>}{<q>} <Rt>, [<Rn>, #{+}<Rm>] ; T1  in strh()
12058       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in strh()
12061                    (rm.GetCode() << 6));  in strh()
12066       // STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1  in strh()
12068           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strh()
12071                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strh()
12075       // STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1  in strh()
12077           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strh()
12080                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strh()
12084       // STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1  in strh()
12086           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strh()
12089                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strh()
12098     Register rm = operand.GetOffsetRegister();  in strh()  local
12102       // STRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}] ; T2  in strh()
12105           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strh()
12107                    rm.GetCode() | (amount << 4));  in strh()
12218     Register rm = operand.GetBaseRegister();  in sub()  local
12221         // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1  in sub()
12223             rm.IsLow()) {  in sub()
12225                      (rm.GetCode() << 6));  in sub()
12229         // SUB{<c>} {<Rd>}, SP, <Rm> ; T1  in sub()
12230         if (rn.Is(sp) && ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sub()
12231           EmitT32_32(0xebad0000U | (rd.GetCode() << 8) | rm.GetCode());  in sub()
12240       // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in sub()
12242           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sub()
12245                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in sub()
12250       // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1  in sub()
12252           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sub()
12254         EmitT32_32(0xebad0000U | (rd.GetCode() << 8) | rm.GetCode() |  in sub()
12261       // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in sub()
12265                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sub()
12269       // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1  in sub()
12273                 (rd.GetCode() << 12) | rm.GetCode() |  in sub()
12280     Register rm = operand.GetBaseRegister();  in sub()  local
12284       // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in sub()
12286           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in sub()
12289                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sub()
12385     Register rm = operand.GetBaseRegister();  in subs()  local
12388         // SUBS{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in subs()
12390             rm.IsLow()) {  in subs()
12392                      (rm.GetCode() << 6));  in subs()
12401       // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2  in subs()
12403           !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in subs()
12406                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in subs()
12411       // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1  in subs()
12413           !rd.Is(pc) && (!rm.IsPC() || AllowUnpredictable())) {  in subs()
12415         EmitT32_32(0xebbd0000U | (rd.GetCode() << 8) | rm.GetCode() |  in subs()
12422       // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1  in subs()
12426                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in subs()
12430       // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1  in subs()
12434                 (rd.GetCode() << 12) | rm.GetCode() |  in subs()
12441     Register rm = operand.GetBaseRegister();  in subs()  local
12445       // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1  in subs()
12447           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in subs()
12450                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in subs()
12532     Register rm = operand.GetBaseRegister();  in sxtab()  local
12536       // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1  in sxtab()
12539           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtab()
12542                    rm.GetCode() | (amount_ << 4));  in sxtab()
12547       // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1  in sxtab()
12550           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtab()
12553                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sxtab()
12569     Register rm = operand.GetBaseRegister();  in sxtab16()  local
12573       // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1  in sxtab16()
12576           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtab16()
12579                    rm.GetCode() | (amount_ << 4));  in sxtab16()
12584       // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1  in sxtab16()
12587           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtab16()
12590                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sxtab16()
12606     Register rm = operand.GetBaseRegister();  in sxtah()  local
12610       // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1  in sxtah()
12613           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtah()
12616                    rm.GetCode() | (amount_ << 4));  in sxtah()
12621       // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1  in sxtah()
12624           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtah()
12627                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sxtah()
12643     Register rm = operand.GetBaseRegister();  in sxtb()  local
12646         // SXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1  in sxtb()
12647         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in sxtb()
12648           EmitT32_16(0xb240 | rd.GetCode() | (rm.GetCode() << 3));  in sxtb()
12657       // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2  in sxtb()
12660           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtb()
12662         EmitT32_32(0xfa4ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in sxtb()
12668       // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1  in sxtb()
12671           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtb()
12674                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in sxtb()
12686     Register rm = operand.GetBaseRegister();  in sxtb16()  local
12690       // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1  in sxtb16()
12693           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtb16()
12695         EmitT32_32(0xfa2ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in sxtb16()
12701       // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1  in sxtb16()
12704           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtb16()
12707                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in sxtb16()
12722     Register rm = operand.GetBaseRegister();  in sxth()  local
12725         // SXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1  in sxth()
12726         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in sxth()
12727           EmitT32_16(0xb200 | rd.GetCode() | (rm.GetCode() << 3));  in sxth()
12736       // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2  in sxth()
12739           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxth()
12741         EmitT32_32(0xfa0ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in sxth()
12747       // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1  in sxth()
12750           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxth()
12753                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in sxth()
12761 void Assembler::tbb(Condition cond, Register rn, Register rm) {  in tbb()  argument
12765     // TBB{<c>}{<q>} [<Rn>, <Rm>] ; T1  in tbb()
12767         (!rm.IsPC() || AllowUnpredictable())) {  in tbb()
12768       EmitT32_32(0xe8d0f000U | (rn.GetCode() << 16) | rm.GetCode());  in tbb()
12773   Delegate(kTbb, &Assembler::tbb, cond, rn, rm);  in tbb()
12776 void Assembler::tbh(Condition cond, Register rn, Register rm) {  in tbh()  argument
12780     // TBH{<c>}{<q>} [<Rn>, <Rm>, LSL #1] ; T1  in tbh()
12782         (!rm.IsPC() || AllowUnpredictable())) {  in tbh()
12783       EmitT32_32(0xe8d0f010U | (rn.GetCode() << 16) | rm.GetCode());  in tbh()
12788   Delegate(kTbh, &Assembler::tbh, cond, rn, rm);  in tbh()
12818     Register rm = operand.GetBaseRegister();  in teq()  local
12822       // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T1  in teq()
12824           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in teq()
12826         EmitT32_32(0xea900f00U | (rn.GetCode() << 16) | rm.GetCode() |  in teq()
12833       // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1  in teq()
12837                 (rn.GetCode() << 16) | rm.GetCode() |  in teq()
12844     Register rm = operand.GetBaseRegister();  in teq()  local
12848       // TEQ{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1  in teq()
12850           ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in teq()
12852                 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |  in teq()
12892     Register rm = operand.GetBaseRegister();  in tst()  local
12895         // TST{<c>}{<q>} <Rn>, <Rm> ; T1  in tst()
12896         if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {  in tst()
12897           EmitT32_16(0x4200 | rn.GetCode() | (rm.GetCode() << 3));  in tst()
12906       // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T2  in tst()
12908           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in tst()
12910         EmitT32_32(0xea100f00U | (rn.GetCode() << 16) | rm.GetCode() |  in tst()
12917       // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1  in tst()
12921                 (rn.GetCode() << 16) | rm.GetCode() |  in tst()
12928     Register rm = operand.GetBaseRegister();  in tst()  local
12932       // TST{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1  in tst()
12934           ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in tst()
12936                 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |  in tst()
12945 void Assembler::uadd16(Condition cond, Register rd, Register rn, Register rm) {  in uadd16()  argument
12949     // UADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uadd16()
12950     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uadd16()
12952                  rm.GetCode());  in uadd16()
12957     // UADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uadd16()
12959         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uadd16()
12961               (rn.GetCode() << 16) | rm.GetCode());  in uadd16()
12965   Delegate(kUadd16, &Assembler::uadd16, cond, rd, rn, rm);  in uadd16()
12968 void Assembler::uadd8(Condition cond, Register rd, Register rn, Register rm) {  in uadd8()  argument
12972     // UADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uadd8()
12973     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uadd8()
12975                  rm.GetCode());  in uadd8()
12980     // UADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uadd8()
12982         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uadd8()
12984               (rn.GetCode() << 16) | rm.GetCode());  in uadd8()
12988   Delegate(kUadd8, &Assembler::uadd8, cond, rd, rn, rm);  in uadd8()
12991 void Assembler::uasx(Condition cond, Register rd, Register rn, Register rm) {  in uasx()  argument
12995     // UASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uasx()
12996     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uasx()
12998                  rm.GetCode());  in uasx()
13003     // UASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uasx()
13005         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uasx()
13007               (rn.GetCode() << 16) | rm.GetCode());  in uasx()
13011   Delegate(kUasx, &Assembler::uasx, cond, rd, rn, rm);  in uasx()
13075 void Assembler::udiv(Condition cond, Register rd, Register rn, Register rm) {  in udiv()  argument
13079     // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in udiv()
13080     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in udiv()
13082                  rm.GetCode());  in udiv()
13087     // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in udiv()
13089         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in udiv()
13091               rn.GetCode() | (rm.GetCode() << 8));  in udiv()
13095   Delegate(kUdiv, &Assembler::udiv, cond, rd, rn, rm);  in udiv()
13098 void Assembler::uhadd16(Condition cond, Register rd, Register rn, Register rm) {  in uhadd16()  argument
13102     // UHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uhadd16()
13103     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhadd16()
13105                  rm.GetCode());  in uhadd16()
13110     // UHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uhadd16()
13112         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhadd16()
13114               (rn.GetCode() << 16) | rm.GetCode());  in uhadd16()
13118   Delegate(kUhadd16, &Assembler::uhadd16, cond, rd, rn, rm);  in uhadd16()
13121 void Assembler::uhadd8(Condition cond, Register rd, Register rn, Register rm) {  in uhadd8()  argument
13125     // UHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uhadd8()
13126     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhadd8()
13128                  rm.GetCode());  in uhadd8()
13133     // UHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uhadd8()
13135         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhadd8()
13137               (rn.GetCode() << 16) | rm.GetCode());  in uhadd8()
13141   Delegate(kUhadd8, &Assembler::uhadd8, cond, rd, rn, rm);  in uhadd8()
13144 void Assembler::uhasx(Condition cond, Register rd, Register rn, Register rm) {  in uhasx()  argument
13148     // UHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uhasx()
13149     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhasx()
13151                  rm.GetCode());  in uhasx()
13156     // UHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uhasx()
13158         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhasx()
13160               (rn.GetCode() << 16) | rm.GetCode());  in uhasx()
13164   Delegate(kUhasx, &Assembler::uhasx, cond, rd, rn, rm);  in uhasx()
13167 void Assembler::uhsax(Condition cond, Register rd, Register rn, Register rm) {  in uhsax()  argument
13171     // UHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uhsax()
13172     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsax()
13174                  rm.GetCode());  in uhsax()
13179     // UHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uhsax()
13181         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsax()
13183               (rn.GetCode() << 16) | rm.GetCode());  in uhsax()
13187   Delegate(kUhsax, &Assembler::uhsax, cond, rd, rn, rm);  in uhsax()
13190 void Assembler::uhsub16(Condition cond, Register rd, Register rn, Register rm) {  in uhsub16()  argument
13194     // UHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uhsub16()
13195     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsub16()
13197                  rm.GetCode());  in uhsub16()
13202     // UHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uhsub16()
13204         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsub16()
13206               (rn.GetCode() << 16) | rm.GetCode());  in uhsub16()
13210   Delegate(kUhsub16, &Assembler::uhsub16, cond, rd, rn, rm);  in uhsub16()
13213 void Assembler::uhsub8(Condition cond, Register rd, Register rn, Register rm) {  in uhsub8()  argument
13217     // UHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uhsub8()
13218     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsub8()
13220                  rm.GetCode());  in uhsub8()
13225     // UHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uhsub8()
13227         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsub8()
13229               (rn.GetCode() << 16) | rm.GetCode());  in uhsub8()
13233   Delegate(kUhsub8, &Assembler::uhsub8, cond, rd, rn, rm);  in uhsub8()
13237     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umaal()  argument
13241     // UMAAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in umaal()
13242     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umaal()
13245                  (rn.GetCode() << 16) | rm.GetCode());  in umaal()
13250     // UMAAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in umaal()
13252         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umaal()
13256               (rm.GetCode() << 8));  in umaal()
13260   Delegate(kUmaal, &Assembler::umaal, cond, rdlo, rdhi, rn, rm);  in umaal()
13264     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umlal()  argument
13268     // UMLAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in umlal()
13269     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umlal()
13272                  (rn.GetCode() << 16) | rm.GetCode());  in umlal()
13277     // UMLAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in umlal()
13279         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umlal()
13283               (rm.GetCode() << 8));  in umlal()
13287   Delegate(kUmlal, &Assembler::umlal, cond, rdlo, rdhi, rn, rm);  in umlal()
13291     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umlals()  argument
13295     // UMLALS{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in umlals()
13297         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umlals()
13301               (rm.GetCode() << 8));  in umlals()
13305   Delegate(kUmlals, &Assembler::umlals, cond, rdlo, rdhi, rn, rm);  in umlals()
13309     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umull()  argument
13313     // UMULL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1  in umull()
13314     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umull()
13317                  (rn.GetCode() << 16) | rm.GetCode());  in umull()
13322     // UMULL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in umull()
13324         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umull()
13328               (rm.GetCode() << 8));  in umull()
13332   Delegate(kUmull, &Assembler::umull, cond, rdlo, rdhi, rn, rm);  in umull()
13336     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umulls()  argument
13340     // UMULLS{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1  in umulls()
13342         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umulls()
13346               (rm.GetCode() << 8));  in umulls()
13350   Delegate(kUmulls, &Assembler::umulls, cond, rdlo, rdhi, rn, rm);  in umulls()
13353 void Assembler::uqadd16(Condition cond, Register rd, Register rn, Register rm) {  in uqadd16()  argument
13357     // UQADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uqadd16()
13358     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqadd16()
13360                  rm.GetCode());  in uqadd16()
13365     // UQADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uqadd16()
13367         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqadd16()
13369               (rn.GetCode() << 16) | rm.GetCode());  in uqadd16()
13373   Delegate(kUqadd16, &Assembler::uqadd16, cond, rd, rn, rm);  in uqadd16()
13376 void Assembler::uqadd8(Condition cond, Register rd, Register rn, Register rm) {  in uqadd8()  argument
13380     // UQADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uqadd8()
13381     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqadd8()
13383                  rm.GetCode());  in uqadd8()
13388     // UQADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uqadd8()
13390         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqadd8()
13392               (rn.GetCode() << 16) | rm.GetCode());  in uqadd8()
13396   Delegate(kUqadd8, &Assembler::uqadd8, cond, rd, rn, rm);  in uqadd8()
13399 void Assembler::uqasx(Condition cond, Register rd, Register rn, Register rm) {  in uqasx()  argument
13403     // UQASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uqasx()
13404     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqasx()
13406                  rm.GetCode());  in uqasx()
13411     // UQASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uqasx()
13413         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqasx()
13415               (rn.GetCode() << 16) | rm.GetCode());  in uqasx()
13419   Delegate(kUqasx, &Assembler::uqasx, cond, rd, rn, rm);  in uqasx()
13422 void Assembler::uqsax(Condition cond, Register rd, Register rn, Register rm) {  in uqsax()  argument
13426     // UQSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uqsax()
13427     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsax()
13429                  rm.GetCode());  in uqsax()
13434     // UQSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uqsax()
13436         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsax()
13438               (rn.GetCode() << 16) | rm.GetCode());  in uqsax()
13442   Delegate(kUqsax, &Assembler::uqsax, cond, rd, rn, rm);  in uqsax()
13445 void Assembler::uqsub16(Condition cond, Register rd, Register rn, Register rm) {  in uqsub16()  argument
13449     // UQSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uqsub16()
13450     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsub16()
13452                  rm.GetCode());  in uqsub16()
13457     // UQSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uqsub16()
13459         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsub16()
13461               (rn.GetCode() << 16) | rm.GetCode());  in uqsub16()
13465   Delegate(kUqsub16, &Assembler::uqsub16, cond, rd, rn, rm);  in uqsub16()
13468 void Assembler::uqsub8(Condition cond, Register rd, Register rn, Register rm) {  in uqsub8()  argument
13472     // UQSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in uqsub8()
13473     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsub8()
13475                  rm.GetCode());  in uqsub8()
13480     // UQSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in uqsub8()
13482         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsub8()
13484               (rn.GetCode() << 16) | rm.GetCode());  in uqsub8()
13488   Delegate(kUqsub8, &Assembler::uqsub8, cond, rd, rn, rm);  in uqsub8()
13491 void Assembler::usad8(Condition cond, Register rd, Register rn, Register rm) {  in usad8()  argument
13495     // USAD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in usad8()
13496     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usad8()
13498                  rm.GetCode());  in usad8()
13503     // USAD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in usad8()
13505         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usad8()
13507               rn.GetCode() | (rm.GetCode() << 8));  in usad8()
13511   Delegate(kUsad8, &Assembler::usad8, cond, rd, rn, rm);  in usad8()
13515     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in usada8()  argument
13519     // USADA8{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1  in usada8()
13521         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usada8()
13523                  rm.GetCode() | (ra.GetCode() << 12));  in usada8()
13528     // USADA8{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1  in usada8()
13530         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usada8()
13532               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in usada8()
13536   Delegate(kUsada8, &Assembler::usada8, cond, rd, rn, rm, ra);  in usada8()
13615 void Assembler::usax(Condition cond, Register rd, Register rn, Register rm) {  in usax()  argument
13619     // USAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in usax()
13620     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usax()
13622                  rm.GetCode());  in usax()
13627     // USAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in usax()
13629         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usax()
13631               (rn.GetCode() << 16) | rm.GetCode());  in usax()
13635   Delegate(kUsax, &Assembler::usax, cond, rd, rn, rm);  in usax()
13638 void Assembler::usub16(Condition cond, Register rd, Register rn, Register rm) {  in usub16()  argument
13642     // USUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in usub16()
13643     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usub16()
13645                  rm.GetCode());  in usub16()
13650     // USUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in usub16()
13652         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usub16()
13654               (rn.GetCode() << 16) | rm.GetCode());  in usub16()
13658   Delegate(kUsub16, &Assembler::usub16, cond, rd, rn, rm);  in usub16()
13661 void Assembler::usub8(Condition cond, Register rd, Register rn, Register rm) {  in usub8()  argument
13665     // USUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1  in usub8()
13666     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usub8()
13668                  rm.GetCode());  in usub8()
13673     // USUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1  in usub8()
13675         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usub8()
13677               (rn.GetCode() << 16) | rm.GetCode());  in usub8()
13681   Delegate(kUsub8, &Assembler::usub8, cond, rd, rn, rm);  in usub8()
13691     Register rm = operand.GetBaseRegister();  in uxtab()  local
13695       // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1  in uxtab()
13698           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtab()
13701                    rm.GetCode() | (amount_ << 4));  in uxtab()
13706       // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1  in uxtab()
13709           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtab()
13712                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in uxtab()
13728     Register rm = operand.GetBaseRegister();  in uxtab16()  local
13732       // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1  in uxtab16()
13735           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtab16()
13738                    rm.GetCode() | (amount_ << 4));  in uxtab16()
13743       // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1  in uxtab16()
13746           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtab16()
13749                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in uxtab16()
13765     Register rm = operand.GetBaseRegister();  in uxtah()  local
13769       // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1  in uxtah()
13772           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtah()
13775                    rm.GetCode() | (amount_ << 4));  in uxtah()
13780       // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1  in uxtah()
13783           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtah()
13786                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in uxtah()
13802     Register rm = operand.GetBaseRegister();  in uxtb()  local
13805         // UXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1  in uxtb()
13806         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in uxtb()
13807           EmitT32_16(0xb2c0 | rd.GetCode() | (rm.GetCode() << 3));  in uxtb()
13816       // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2  in uxtb()
13819           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtb()
13821         EmitT32_32(0xfa5ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in uxtb()
13827       // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1  in uxtb()
13830           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtb()
13833                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in uxtb()
13845     Register rm = operand.GetBaseRegister();  in uxtb16()  local
13849       // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1  in uxtb16()
13852           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtb16()
13854         EmitT32_32(0xfa3ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in uxtb16()
13860       // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1  in uxtb16()
13863           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtb16()
13866                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in uxtb16()
13881     Register rm = operand.GetBaseRegister();  in uxth()  local
13884         // UXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1  in uxth()
13885         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in uxth()
13886           EmitT32_16(0xb280 | rd.GetCode() | (rm.GetCode() << 3));  in uxth()
13895       // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2  in uxth()
13898           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxth()
13900         EmitT32_32(0xfa1ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in uxth()
13906       // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1  in uxth()
13909           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxth()
13912                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in uxth()
13921     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vaba()  argument
13931                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaba()
13942                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaba()
13947   Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);  in vaba()
13951     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vaba()  argument
13961                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaba()
13972                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaba()
13977   Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);  in vaba()
13981     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vabal()  argument
13991                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabal()
14002                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabal()
14007   Delegate(kVabal, &Assembler::vabal, cond, dt, rd, rn, rm);  in vabal()
14011     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vabd()  argument
14020                    rm.Encode(5, 0));  in vabd()
14030                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabd()
14040                 rm.Encode(5, 0));  in vabd()
14049                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabd()
14054   Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);  in vabd()
14058     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vabd()  argument
14067                    rm.Encode(5, 0));  in vabd()
14077                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabd()
14087                 rm.Encode(5, 0));  in vabd()
14096                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabd()
14101   Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);  in vabd()
14105     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vabdl()  argument
14115                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabdl()
14126                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabdl()
14131   Delegate(kVabdl, &Assembler::vabdl, cond, dt, rd, rn, rm);  in vabdl()
14134 void Assembler::vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vabs()  argument
14144                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14151       EmitT32_32(0xeeb00bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14161                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14168               rm.Encode(5, 0));  in vabs()
14172   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);  in vabs()
14175 void Assembler::vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vabs()  argument
14185                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14196                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14201   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);  in vabs()
14204 void Assembler::vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) {  in vabs()  argument
14210       EmitT32_32(0xeeb00ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14218               rm.Encode(5, 0));  in vabs()
14222   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);  in vabs()
14226     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vacge()  argument
14234                    rm.Encode(5, 0));  in vacge()
14244                 rm.Encode(5, 0));  in vacge()
14249   Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);  in vacge()
14253     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vacge()  argument
14261                    rm.Encode(5, 0));  in vacge()
14271                 rm.Encode(5, 0));  in vacge()
14276   Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);  in vacge()
14280     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vacgt()  argument
14288                    rm.Encode(5, 0));  in vacgt()
14298                 rm.Encode(5, 0));  in vacgt()
14303   Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);  in vacgt()
14307     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vacgt()  argument
14315                    rm.Encode(5, 0));  in vacgt()
14325                 rm.Encode(5, 0));  in vacgt()
14330   Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);  in vacgt()
14334     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vacle()  argument
14342                    rm.Encode(5, 0));  in vacle()
14352                 rm.Encode(5, 0));  in vacle()
14357   Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);  in vacle()
14361     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vacle()  argument
14369                    rm.Encode(5, 0));  in vacle()
14379                 rm.Encode(5, 0));  in vacle()
14384   Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);  in vacle()
14388     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vaclt()  argument
14396                    rm.Encode(5, 0));  in vaclt()
14406                 rm.Encode(5, 0));  in vaclt()
14411   Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);  in vaclt()
14415     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vaclt()  argument
14423                    rm.Encode(5, 0));  in vaclt()
14433                 rm.Encode(5, 0));  in vaclt()
14438   Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);  in vaclt()
14442     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vadd()  argument
14451                    rm.Encode(5, 0));  in vadd()
14459                  rm.Encode(5, 0));  in vadd()
14467                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14477                 rm.Encode(5, 0));  in vadd()
14484               rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14491                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14496   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);  in vadd()
14500     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vadd()  argument
14509                    rm.Encode(5, 0));  in vadd()
14518                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14528                 rm.Encode(5, 0));  in vadd()
14536                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14541   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);  in vadd()
14545     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vadd()  argument
14552                  rm.Encode(5, 0));  in vadd()
14560               rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14564   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);  in vadd()
14568     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {  in vaddhn()  argument
14577                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddhn()
14587                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddhn()
14592   Delegate(kVaddhn, &Assembler::vaddhn, cond, dt, rd, rn, rm);  in vaddhn()
14596     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vaddl()  argument
14606                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddl()
14617                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddl()
14622   Delegate(kVaddl, &Assembler::vaddl, cond, dt, rd, rn, rm);  in vaddl()
14626     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {  in vaddw()  argument
14636                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddw()
14647                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddw()
14652   Delegate(kVaddw, &Assembler::vaddw, cond, dt, rd, rn, rm);  in vaddw()
14691     DRegister rm = operand.GetRegister();  in vand()  local
14697                    rm.Encode(5, 0));  in vand()
14705                 rm.Encode(5, 0));  in vand()
14749     QRegister rm = operand.GetRegister();  in vand()  local
14755                    rm.Encode(5, 0));  in vand()
14763                 rm.Encode(5, 0));  in vand()
14807     DRegister rm = operand.GetRegister();  in vbic()  local
14813                    rm.Encode(5, 0));  in vbic()
14821                 rm.Encode(5, 0));  in vbic()
14865     QRegister rm = operand.GetRegister();  in vbic()  local
14871                    rm.Encode(5, 0));  in vbic()
14879                 rm.Encode(5, 0));  in vbic()
14888     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vbif()  argument
14896                  rm.Encode(5, 0));  in vbif()
14904               rm.Encode(5, 0));  in vbif()
14908   Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);  in vbif()
14912     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vbif()  argument
14920                  rm.Encode(5, 0));  in vbif()
14928               rm.Encode(5, 0));  in vbif()
14932   Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);  in vbif()
14936     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vbit()  argument
14944                  rm.Encode(5, 0));  in vbit()
14952               rm.Encode(5, 0));  in vbit()
14956   Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);  in vbit()
14960     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vbit()  argument
14968                  rm.Encode(5, 0));  in vbit()
14976               rm.Encode(5, 0));  in vbit()
14980   Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);  in vbit()
14984     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vbsl()  argument
14992                  rm.Encode(5, 0));  in vbsl()
15000               rm.Encode(5, 0));  in vbsl()
15004   Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);  in vbsl()
15008     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vbsl()  argument
15016                  rm.Encode(5, 0));  in vbsl()
15024               rm.Encode(5, 0));  in vbsl()
15028   Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);  in vbsl()
15034                      DRegister rm,  in vceq()  argument
15049                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vceq()
15061                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vceq()
15068   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);  in vceq()
15074                      QRegister rm,  in vceq()  argument
15089                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vceq()
15101                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vceq()
15108   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);  in vceq()
15112     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vceq()  argument
15122                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15131                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15141                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15149                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15154   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);  in vceq()
15158     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vceq()  argument
15168                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15177                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15187                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15195                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15200   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);  in vceq()
15206                      DRegister rm,  in vcge()  argument
15221                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcge()
15233                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcge()
15240   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);  in vcge()
15246                      QRegister rm,  in vcge()  argument
15261                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcge()
15273                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcge()
15280   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);  in vcge()
15284     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vcge()  argument
15294                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcge()
15303                    rm.Encode(5, 0));  in vcge()
15314                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcge()
15322                 rm.Encode(5, 0));  in vcge()
15327   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);  in vcge()
15331     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vcge()  argument
15341                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcge()
15350                    rm.Encode(5, 0));  in vcge()
15361                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcge()
15369                 rm.Encode(5, 0));  in vcge()
15374   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);  in vcge()
15380                      DRegister rm,  in vcgt()  argument
15395                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcgt()
15407                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcgt()
15414   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);  in vcgt()
15420                      QRegister rm,  in vcgt()  argument
15435                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcgt()
15447                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcgt()
15454   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);  in vcgt()
15458     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vcgt()  argument
15468                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcgt()
15477                    rm.Encode(5, 0));  in vcgt()
15488                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcgt()
15496                 rm.Encode(5, 0));  in vcgt()
15501   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);  in vcgt()
15505     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vcgt()  argument
15515                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcgt()
15524                    rm.Encode(5, 0));  in vcgt()
15535                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcgt()
15543                 rm.Encode(5, 0));  in vcgt()
15548   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);  in vcgt()
15554                      DRegister rm,  in vcle()  argument
15569                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcle()
15581                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcle()
15588   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);  in vcle()
15594                      QRegister rm,  in vcle()  argument
15609                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcle()
15621                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcle()
15628   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);  in vcle()
15632     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vcle()  argument
15642                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vcle()
15651                    rm.Encode(7, 16));  in vcle()
15662                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vcle()
15670                 rm.Encode(7, 16));  in vcle()
15675   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);  in vcle()
15679     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vcle()  argument
15689                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vcle()
15698                    rm.Encode(7, 16));  in vcle()
15709                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vcle()
15717                 rm.Encode(7, 16));  in vcle()
15722   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);  in vcle()
15725 void Assembler::vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vcls()  argument
15734                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vcls()
15744                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vcls()
15749   Delegate(kVcls, &Assembler::vcls, cond, dt, rd, rm);  in vcls()
15752 void Assembler::vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vcls()  argument
15761                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vcls()
15771                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vcls()
15776   Delegate(kVcls, &Assembler::vcls, cond, dt, rd, rm);  in vcls()
15782                      DRegister rm,  in vclt()  argument
15797                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vclt()
15809                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vclt()
15816   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);  in vclt()
15822                      QRegister rm,  in vclt()  argument
15837                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vclt()
15849                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vclt()
15856   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);  in vclt()
15860     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vclt()  argument
15870                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vclt()
15879                    rm.Encode(7, 16));  in vclt()
15890                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vclt()
15898                 rm.Encode(7, 16));  in vclt()
15903   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);  in vclt()
15907     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vclt()  argument
15917                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vclt()
15926                    rm.Encode(7, 16));  in vclt()
15937                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vclt()
15945                 rm.Encode(7, 16));  in vclt()
15950   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);  in vclt()
15953 void Assembler::vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vclz()  argument
15962                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vclz()
15972                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vclz()
15977   Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);  in vclz()
15980 void Assembler::vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vclz()  argument
15989                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vclz()
15999                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vclz()
16004   Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);  in vclz()
16014     SRegister rm = operand.GetRegister();  in vcmp()  local
16018         EmitT32_32(0xeeb40a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcmp()
16026                 rm.Encode(5, 0));  in vcmp()
16057     DRegister rm = operand.GetRegister();  in vcmp()  local
16061         EmitT32_32(0xeeb40b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcmp()
16069                 rm.Encode(5, 0));  in vcmp()
16100     SRegister rm = operand.GetRegister();  in vcmpe()  local
16104         EmitT32_32(0xeeb40ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcmpe()
16112                 rm.Encode(5, 0));  in vcmpe()
16143     DRegister rm = operand.GetRegister();  in vcmpe()  local
16147         EmitT32_32(0xeeb40bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcmpe()
16155                 rm.Encode(5, 0));  in vcmpe()
16179 void Assembler::vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vcnt()  argument
16186         EmitT32_32(0xffb00500U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcnt()
16195         EmitA32(0xf3b00500U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcnt()
16200   Delegate(kVcnt, &Assembler::vcnt, cond, dt, rd, rm);  in vcnt()
16203 void Assembler::vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vcnt()  argument
16210         EmitT32_32(0xffb00540U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcnt()
16219         EmitA32(0xf3b00540U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcnt()
16224   Delegate(kVcnt, &Assembler::vcnt, cond, dt, rd, rm);  in vcnt()
16228     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {  in vcvt()  argument
16235       EmitT32_32(0xeeb70ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16242                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16250               rm.Encode(5, 0));  in vcvt()
16257               rm.Encode(5, 0));  in vcvt()
16261   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16265     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvt()  argument
16271       EmitT32_32(0xeeb70bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16277       EmitT32_32(0xeebc0bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16283       EmitT32_32(0xeebd0bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16291               rm.Encode(5, 0));  in vcvt()
16297               rm.Encode(5, 0));  in vcvt()
16303               rm.Encode(5, 0));  in vcvt()
16307   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16314                      DRegister rm,  in vcvt()  argument
16328                    rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));  in vcvt()
16334     if (dt1.Is(F64) && encoded_dt_2.IsValid() && rd.Is(rm) &&  in vcvt()
16350     if (encoded_dt_3.IsValid() && dt2.Is(F64) && rd.Is(rm) &&  in vcvt()
16372                 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));  in vcvt()
16377     if (dt1.Is(F64) && encoded_dt_2.IsValid() && rd.Is(rm) &&  in vcvt()
16394     if (encoded_dt_3.IsValid() && dt2.Is(F64) && rd.Is(rm) &&  in vcvt()
16411   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);  in vcvt()
16418                      QRegister rm,  in vcvt()  argument
16430                    rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));  in vcvt()
16442                 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));  in vcvt()
16447   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);  in vcvt()
16454                      SRegister rm,  in vcvt()  argument
16462     if (dt1.Is(F32) && encoded_dt.IsValid() && rd.Is(rm) &&  in vcvt()
16478     if (encoded_dt_2.IsValid() && dt2.Is(F32) && rd.Is(rm) &&  in vcvt()
16495     if (dt1.Is(F32) && encoded_dt.IsValid() && rd.Is(rm) &&  in vcvt()
16512     if (encoded_dt_2.IsValid() && dt2.Is(F32) && rd.Is(rm) &&  in vcvt()
16529   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);  in vcvt()
16533     Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvt()  argument
16542                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16552                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16557   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16561     Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvt()  argument
16570                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16580                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16585   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16589     Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) {  in vcvt()  argument
16596         EmitT32_32(0xffb60600U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16605         EmitA32(0xf3b60600U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16610   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16614     Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) {  in vcvt()  argument
16621         EmitT32_32(0xffb60700U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16630         EmitA32(0xf3b60700U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16635   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16639     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvt()  argument
16646       EmitT32_32(0xeebc0ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16652       EmitT32_32(0xeebd0ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16659                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16667               rm.Encode(5, 0));  in vcvt()
16673               rm.Encode(5, 0));  in vcvt()
16680               rm.Encode(5, 0));  in vcvt()
16684   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16687 void Assembler::vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvta()  argument
16695                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16703               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16707   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);  in vcvta()
16710 void Assembler::vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvta()  argument
16718                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16726               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16730   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);  in vcvta()
16733 void Assembler::vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvta()  argument
16741                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16749               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16753   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);  in vcvta()
16756 void Assembler::vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvta()  argument
16764                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16772               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16776   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);  in vcvta()
16780     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtb()  argument
16786       EmitT32_32(0xeeb20a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtb()
16792       EmitT32_32(0xeeb30a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtb()
16800               rm.Encode(5, 0));  in vcvtb()
16806               rm.Encode(5, 0));  in vcvtb()
16810   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);  in vcvtb()
16814     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {  in vcvtb()  argument
16820       EmitT32_32(0xeeb20b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtb()
16828               rm.Encode(5, 0));  in vcvtb()
16832   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);  in vcvtb()
16836     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtb()  argument
16842       EmitT32_32(0xeeb30b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtb()
16850               rm.Encode(5, 0));  in vcvtb()
16854   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);  in vcvtb()
16857 void Assembler::vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvtm()  argument
16865                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16873               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16877   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);  in vcvtm()
16880 void Assembler::vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvtm()  argument
16888                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16896               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16900   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);  in vcvtm()
16903 void Assembler::vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtm()  argument
16911                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16919               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16923   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);  in vcvtm()
16926 void Assembler::vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtm()  argument
16934                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16942               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16946   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);  in vcvtm()
16949 void Assembler::vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvtn()  argument
16957                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16965               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16969   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);  in vcvtn()
16972 void Assembler::vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvtn()  argument
16980                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16988               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16992   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);  in vcvtn()
16995 void Assembler::vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtn()  argument
17003                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
17011               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
17015   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);  in vcvtn()
17018 void Assembler::vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtn()  argument
17026                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
17034               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
17038   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);  in vcvtn()
17041 void Assembler::vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvtp()  argument
17049                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17057               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17061   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);  in vcvtp()
17064 void Assembler::vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvtp()  argument
17072                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17080               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17084   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);  in vcvtp()
17087 void Assembler::vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtp()  argument
17095                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17103               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17107   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);  in vcvtp()
17110 void Assembler::vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtp()  argument
17118                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17126               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17130   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);  in vcvtp()
17134     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtr()  argument
17140       EmitT32_32(0xeebc0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtr()
17146       EmitT32_32(0xeebd0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtr()
17154               rm.Encode(5, 0));  in vcvtr()
17160               rm.Encode(5, 0));  in vcvtr()
17164   Delegate(kVcvtr, &Assembler::vcvtr, cond, dt1, dt2, rd, rm);  in vcvtr()
17168     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtr()  argument
17174       EmitT32_32(0xeebc0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtr()
17180       EmitT32_32(0xeebd0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtr()
17188               rm.Encode(5, 0));  in vcvtr()
17194               rm.Encode(5, 0));  in vcvtr()
17198   Delegate(kVcvtr, &Assembler::vcvtr, cond, dt1, dt2, rd, rm);  in vcvtr()
17202     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtt()  argument
17208       EmitT32_32(0xeeb20ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtt()
17214       EmitT32_32(0xeeb30ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtt()
17222               rm.Encode(5, 0));  in vcvtt()
17228               rm.Encode(5, 0));  in vcvtt()
17232   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);  in vcvtt()
17236     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {  in vcvtt()  argument
17242       EmitT32_32(0xeeb20bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtt()
17250               rm.Encode(5, 0));  in vcvtt()
17254   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);  in vcvtt()
17258     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtt()  argument
17264       EmitT32_32(0xeeb30bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtt()
17272               rm.Encode(5, 0));  in vcvtt()
17276   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);  in vcvtt()
17280     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vdiv()  argument
17287                  rm.Encode(5, 0));  in vdiv()
17295               rn.Encode(7, 16) | rm.Encode(5, 0));  in vdiv()
17299   Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);  in vdiv()
17303     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vdiv()  argument
17310                  rm.Encode(5, 0));  in vdiv()
17318               rn.Encode(7, 16) | rm.Encode(5, 0));  in vdiv()
17322   Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);  in vdiv()
17390                      DRegisterLane rm) {  in vdup()  argument
17393   Dt_imm4_1 encoded_dt(dt, rm);  in vdup()
17399                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vdup()
17409                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vdup()
17414   Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rm);  in vdup()
17420                      DRegisterLane rm) {  in vdup()  argument
17423   Dt_imm4_1 encoded_dt(dt, rm);  in vdup()
17429                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vdup()
17439                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vdup()
17444   Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rm);  in vdup()
17448     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in veor()  argument
17456                  rm.Encode(5, 0));  in veor()
17464               rm.Encode(5, 0));  in veor()
17468   Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);  in veor()
17472     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in veor()  argument
17480                  rm.Encode(5, 0));  in veor()
17488               rm.Encode(5, 0));  in veor()
17492   Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);  in veor()
17499                      DRegister rm,  in vext()  argument
17511                        rm.Encode(5, 0) | (imm << 8));  in vext()
17522                        rm.Encode(5, 0) | (imm4 << 8));  in vext()
17532                     rm.Encode(5, 0) | (imm << 8));  in vext()
17542                     rm.Encode(5, 0) | (imm4 << 8));  in vext()
17549   Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);  in vext()
17556                      QRegister rm,  in vext()  argument
17568                        rm.Encode(5, 0) | (imm << 8));  in vext()
17579                        rm.Encode(5, 0) | (imm4 << 8));  in vext()
17589                     rm.Encode(5, 0) | (imm << 8));  in vext()
17599                     rm.Encode(5, 0) | (imm4 << 8));  in vext()
17606   Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);  in vext()
17610     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vfma()  argument
17618                    rm.Encode(5, 0));  in vfma()
17626                  rm.Encode(5, 0));  in vfma()
17635                 rm.Encode(5, 0));  in vfma()
17642               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfma()
17646   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);  in vfma()
17650     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vfma()  argument
17658                    rm.Encode(5, 0));  in vfma()
17668                 rm.Encode(5, 0));  in vfma()
17673   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);  in vfma()
17677     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vfma()  argument
17684                  rm.Encode(5, 0));  in vfma()
17692               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfma()
17696   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);  in vfma()
17700     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vfms()  argument
17708                    rm.Encode(5, 0));  in vfms()
17716                  rm.Encode(5, 0));  in vfms()
17725                 rm.Encode(5, 0));  in vfms()
17732               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfms()
17736   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);  in vfms()
17740     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vfms()  argument
17748                    rm.Encode(5, 0));  in vfms()
17758                 rm.Encode(5, 0));  in vfms()
17763   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);  in vfms()
17767     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vfms()  argument
17774                  rm.Encode(5, 0));  in vfms()
17782               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfms()
17786   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);  in vfms()
17790     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vfnma()  argument
17797                  rm.Encode(5, 0));  in vfnma()
17805               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfnma()
17809   Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);  in vfnma()
17813     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vfnma()  argument
17820                  rm.Encode(5, 0));  in vfnma()
17828               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfnma()
17832   Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);  in vfnma()
17836     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vfnms()  argument
17843                  rm.Encode(5, 0));  in vfnms()
17851               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfnms()
17855   Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);  in vfnms()
17859     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vfnms()  argument
17866                  rm.Encode(5, 0));  in vfnms()
17874               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfnms()
17878   Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);  in vfnms()
17882     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vhadd()  argument
17892                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhadd()
17903                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhadd()
17908   Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);  in vhadd()
17912     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vhadd()  argument
17922                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhadd()
17933                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhadd()
17938   Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);  in vhadd()
17942     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vhsub()  argument
17952                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhsub()
17963                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhsub()
17968   Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);  in vhsub()
17972     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vhsub()  argument
17982                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhsub()
17993                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhsub()
17998   Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);  in vhsub()
18260     Register rm = operand.GetOffsetRegister();  in vld1()  local
18267       // VLD1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld1()
18270           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld1()
18293                      (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18298       // VLD1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld1()
18301           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld1()
18308                      (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18313       // VLD1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld1()
18315           (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&  in vld1()
18322                      rm.GetCode());  in vld1()
18328       // VLD1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld1()
18331           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld1()
18354                   (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18358       // VLD1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld1()
18361           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld1()
18368                   (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18372       // VLD1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld1()
18374           (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&  in vld1()
18380                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18639     Register rm = operand.GetOffsetRegister();  in vld2()  local
18645       // VLD2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld2()
18650           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18666                      (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18671       // VLD2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld2()
18675           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18682                      (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18687       // VLD2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld2()
18691           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18697                      rm.GetCode());  in vld2()
18703       // VLD2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld2()
18708           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18724                   (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18728       // VLD2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld2()
18732           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18739                   (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18743       // VLD2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld2()
18747           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18752                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18845     Register rm = operand.GetOffsetRegister();  in vld3()  local
18849       // VLD3{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld3()
18853           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld3()
18860                      (rn.GetCode() << 16) | rm.GetCode());  in vld3()
18866       // VLD3{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld3()
18870           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld3()
18877                   (rn.GetCode() << 16) | rm.GetCode());  in vld3()
19015     Register rm = operand.GetOffsetRegister();  in vld3()  local
19019       // VLD3{<c>}{<q>}.<dt> <list>, [<Rn>], #<Rm> ; T1  in vld3()
19030                      (rn.GetCode() << 16) | rm.GetCode());  in vld3()
19035       // VLD3{<c>}{<q>}.<dt> <list>, [<Rn>], #<Rm> ; T1  in vld3()
19046                      rm.GetCode());  in vld3()
19052       // VLD3{<c>}{<q>}.<dt> <list>, [<Rn>], #<Rm> ; A1  in vld3()
19063                   (rn.GetCode() << 16) | rm.GetCode());  in vld3()
19067       // VLD3{<c>}{<q>}.<dt> <list>, [<Rn>], #<Rm> ; A1  in vld3()
19077                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vld3()
19297     Register rm = operand.GetOffsetRegister();  in vld4()  local
19304       // VLD4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld4()
19308           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19315                      (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19320       // VLD4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld4()
19324           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19331                      (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19336       // VLD4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vld4()
19340           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19346                      rm.GetCode());  in vld4()
19352       // VLD4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld4()
19356           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19363                   (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19367       // VLD4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld4()
19371           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19378                   (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19382       // VLD4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vld4()
19386           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19391                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19916     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmax()  argument
19925                    rm.Encode(5, 0));  in vmax()
19935                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmax()
19945                 rm.Encode(5, 0));  in vmax()
19954                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmax()
19959   Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);  in vmax()
19963     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmax()  argument
19972                    rm.Encode(5, 0));  in vmax()
19982                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmax()
19992                 rm.Encode(5, 0));  in vmax()
20001                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmax()
20006   Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);  in vmax()
20009 void Assembler::vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmaxnm()  argument
20016                  rm.Encode(5, 0));  in vmaxnm()
20023                  rm.Encode(5, 0));  in vmaxnm()
20031               rm.Encode(5, 0));  in vmaxnm()
20037               rm.Encode(5, 0));  in vmaxnm()
20041   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);  in vmaxnm()
20044 void Assembler::vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmaxnm()  argument
20051                  rm.Encode(5, 0));  in vmaxnm()
20059               rm.Encode(5, 0));  in vmaxnm()
20063   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);  in vmaxnm()
20066 void Assembler::vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vmaxnm()  argument
20073                  rm.Encode(5, 0));  in vmaxnm()
20081               rm.Encode(5, 0));  in vmaxnm()
20085   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);  in vmaxnm()
20089     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmin()  argument
20098                    rm.Encode(5, 0));  in vmin()
20108                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmin()
20118                 rm.Encode(5, 0));  in vmin()
20127                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmin()
20132   Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);  in vmin()
20136     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmin()  argument
20145                    rm.Encode(5, 0));  in vmin()
20155                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmin()
20165                 rm.Encode(5, 0));  in vmin()
20174                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmin()
20179   Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);  in vmin()
20182 void Assembler::vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vminnm()  argument
20189                  rm.Encode(5, 0));  in vminnm()
20196                  rm.Encode(5, 0));  in vminnm()
20204               rm.Encode(5, 0));  in vminnm()
20210               rm.Encode(5, 0));  in vminnm()
20214   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);  in vminnm()
20217 void Assembler::vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vminnm()  argument
20224                  rm.Encode(5, 0));  in vminnm()
20232               rm.Encode(5, 0));  in vminnm()
20236   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);  in vminnm()
20239 void Assembler::vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vminnm()  argument
20246                  rm.Encode(5, 0));  in vminnm()
20254               rm.Encode(5, 0));  in vminnm()
20258   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);  in vminnm()
20262     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {  in vmla()  argument
20269         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmla()
20270          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmla()
20271           (rm.GetLane() <= 1)))) {  in vmla()
20275                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmla()
20283         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmla()
20284          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmla()
20285           (rm.GetLane() <= 1)))) {  in vmla()
20289                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmla()
20294   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20298     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {  in vmla()  argument
20305         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmla()
20306          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmla()
20307           (rm.GetLane() <= 1)))) {  in vmla()
20311                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmla()
20319         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmla()
20320          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmla()
20321           (rm.GetLane() <= 1)))) {  in vmla()
20325                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmla()
20330   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20334     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmla()  argument
20343                    rm.Encode(5, 0));  in vmla()
20351                  rm.Encode(5, 0));  in vmla()
20359                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20369                 rm.Encode(5, 0));  in vmla()
20376               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20383                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20388   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20392     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmla()  argument
20401                    rm.Encode(5, 0));  in vmla()
20410                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20420                 rm.Encode(5, 0));  in vmla()
20428                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20433   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20437     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vmla()  argument
20444                  rm.Encode(5, 0));  in vmla()
20452               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20456   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20460     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {  in vmlal()  argument
20467         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmlal()
20468          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmlal()
20469           (rm.GetLane() <= 1)))) {  in vmlal()
20473                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmlal()
20481         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmlal()
20482          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmlal()
20483           (rm.GetLane() <= 1)))) {  in vmlal()
20487                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmlal()
20492   Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);  in vmlal()
20496     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vmlal()  argument
20506                    rn.Encode(7, 16) | rm.Encode(5, 0));  in vmlal()
20517                 rn.Encode(7, 16) | rm.Encode(5, 0));  in vmlal()
20522   Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);  in vmlal()
20526     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {  in vmls()  argument
20533         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmls()
20534          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmls()
20535           (rm.GetLane() <= 1)))) {  in vmls()
20539                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmls()
20547         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmls()
20548          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmls()
20549           (rm.GetLane() <= 1)))) {  in vmls()
20553                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmls()
20558   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20562     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {  in vmls()  argument
20569         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmls()
20570          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmls()
20571           (rm.GetLane() <= 1)))) {  in vmls()
20575                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmls()
20583         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmls()
20584          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmls()
20585           (rm.GetLane() <= 1)))) {  in vmls()
20589                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmls()
20594   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20598     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmls()  argument
20607                    rm.Encode(5, 0));  in vmls()
20615                  rm.Encode(5, 0));  in vmls()
20623                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20633                 rm.Encode(5, 0));  in vmls()
20640               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20647                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20652   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20656     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmls()  argument
20665                    rm.Encode(5, 0));  in vmls()
20674                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20684                 rm.Encode(5, 0));  in vmls()
20692                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20697   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20701     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vmls()  argument
20708                  rm.Encode(5, 0));  in vmls()
20716               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20720   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20724     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {  in vmlsl()  argument
20731         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmlsl()
20732          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmlsl()
20733           (rm.GetLane() <= 1)))) {  in vmlsl()
20737                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmlsl()
20745         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmlsl()
20746          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmlsl()
20747           (rm.GetLane() <= 1)))) {  in vmlsl()
20751                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmlsl()
20756   Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);  in vmlsl()
20760     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vmlsl()  argument
20770                    rn.Encode(7, 16) | rm.Encode(5, 0));  in vmlsl()
20781                 rn.Encode(7, 16) | rm.Encode(5, 0));  in vmlsl()
20786   Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);  in vmlsl()
20831 void Assembler::vmov(Condition cond, Register rt, Register rt2, DRegister rm) {  in vmov()  argument
20838                  rm.Encode(5, 0));  in vmov()
20847               (rt2.GetCode() << 16) | rm.Encode(5, 0));  in vmov()
20851   Delegate(kVmov, &Assembler::vmov, cond, rt, rt2, rm);  in vmov()
20854 void Assembler::vmov(Condition cond, DRegister rm, Register rt, Register rt2) {  in vmov()  argument
20860       EmitT32_32(0xec400b10U | rm.Encode(5, 0) | (rt.GetCode() << 12) |  in vmov()
20869       EmitA32(0x0c400b10U | (cond.GetCondition() << 28) | rm.Encode(5, 0) |  in vmov()
20874   Delegate(kVmov, &Assembler::vmov, cond, rm, rt, rt2);  in vmov()
20878     Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1) {  in vmov()  argument
20883     if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&  in vmov()
20886                  rm.Encode(5, 0));  in vmov()
20892     if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&  in vmov()
20896               (rt2.GetCode() << 16) | rm.Encode(5, 0));  in vmov()
20900   Delegate(kVmov, &Assembler::vmov, cond, rt, rt2, rm, rm1);  in vmov()
20904     Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2) {  in vmov()  argument
20909     if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&  in vmov()
20911       EmitT32_32(0xec400a10U | rm.Encode(5, 0) | (rt.GetCode() << 12) |  in vmov()
20918     if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&  in vmov()
20921       EmitA32(0x0c400a10U | (cond.GetCondition() << 28) | rm.Encode(5, 0) |  in vmov()
20926   Delegate(kVmov, &Assembler::vmov, cond, rm, rm1, rt, rt2);  in vmov()
21017     DRegister rm = operand.GetRegister();  in vmov()  local
21021         EmitT32_32(0xeeb00b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmov()
21028           EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vmov()
21029                      rm.Encode(5, 0));  in vmov()
21038                 rm.Encode(5, 0));  in vmov()
21044           EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vmov()
21045                   rm.Encode(5, 0));  in vmov()
21091     QRegister rm = operand.GetRegister();  in vmov()  local
21096           EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vmov()
21097                      rm.Encode(5, 0));  in vmov()
21106           EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vmov()
21107                   rm.Encode(5, 0));  in vmov()
21144     SRegister rm = operand.GetRegister();  in vmov()  local
21148         EmitT32_32(0xeeb00a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmov()
21156                 rm.Encode(5, 0));  in vmov()
21196 void Assembler::vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) {  in vmovl()  argument
21206                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vmovl()
21217                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vmovl()
21222   Delegate(kVmovl, &Assembler::vmovl, cond, dt, rd, rm);  in vmovl()
21225 void Assembler::vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {  in vmovn()  argument
21234                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vmovn()
21244                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vmovn()
21249   Delegate(kVmovn, &Assembler::vmovn, cond, dt, rd, rm);  in vmovn()
21396     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmul()  argument
21405                    rm.Encode(5, 0));  in vmul()
21413                  rm.Encode(5, 0));  in vmul()
21422                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21432                 rm.Encode(5, 0));  in vmul()
21439               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21447                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21452   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);  in vmul()
21456     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmul()  argument
21465                    rm.Encode(5, 0));  in vmul()
21475                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21485                 rm.Encode(5, 0));  in vmul()
21494                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21499   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);  in vmul()
21503     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vmul()  argument
21510                  rm.Encode(5, 0));  in vmul()
21518               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21522   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);  in vmul()
21578     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vmull()  argument
21589                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmull()
21601                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmull()
21606   Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, rm);  in vmull()
21644     DRegister rm = operand.GetRegister();  in vmvn()  local
21649         EmitT32_32(0xffb00580U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmvn()
21656         EmitA32(0xf3b00580U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmvn()
21699     QRegister rm = operand.GetRegister();  in vmvn()  local
21704         EmitT32_32(0xffb005c0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmvn()
21711         EmitA32(0xf3b005c0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmvn()
21719 void Assembler::vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vneg()  argument
21729                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21736       EmitT32_32(0xeeb10b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21746                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21753               rm.Encode(5, 0));  in vneg()
21757   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);  in vneg()
21760 void Assembler::vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vneg()  argument
21770                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21781                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21786   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);  in vneg()
21789 void Assembler::vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) {  in vneg()  argument
21795       EmitT32_32(0xeeb10a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21803               rm.Encode(5, 0));  in vneg()
21807   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);  in vneg()
21811     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vnmla()  argument
21818                  rm.Encode(5, 0));  in vnmla()
21826               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmla()
21830   Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);  in vnmla()
21834     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vnmla()  argument
21841                  rm.Encode(5, 0));  in vnmla()
21849               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmla()
21853   Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);  in vnmla()
21857     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vnmls()  argument
21864                  rm.Encode(5, 0));  in vnmls()
21872               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmls()
21876   Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);  in vnmls()
21880     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vnmls()  argument
21887                  rm.Encode(5, 0));  in vnmls()
21895               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmls()
21899   Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);  in vnmls()
21903     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vnmul()  argument
21910                  rm.Encode(5, 0));  in vnmul()
21918               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmul()
21922   Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);  in vnmul()
21926     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vnmul()  argument
21933                  rm.Encode(5, 0));  in vnmul()
21941               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmul()
21945   Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);  in vnmul()
21984     DRegister rm = operand.GetRegister();  in vorn()  local
21990                    rm.Encode(5, 0));  in vorn()
21998                 rm.Encode(5, 0));  in vorn()
22042     QRegister rm = operand.GetRegister();  in vorn()  local
22048                    rm.Encode(5, 0));  in vorn()
22056                 rm.Encode(5, 0));  in vorn()
22072     DRegister rm = operand.GetRegister();  in vorr()  local
22078                    rm.Encode(5, 0));  in vorr()
22086                 rm.Encode(5, 0));  in vorr()
22130     QRegister rm = operand.GetRegister();  in vorr()  local
22136                    rm.Encode(5, 0));  in vorr()
22144                 rm.Encode(5, 0));  in vorr()
22183                        DRegister rm) {  in vpadal()  argument
22193                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vpadal()
22204                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vpadal()
22209   Delegate(kVpadal, &Assembler::vpadal, cond, dt, rd, rm);  in vpadal()
22215                        QRegister rm) {  in vpadal()  argument
22225                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vpadal()
22236                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vpadal()
22241   Delegate(kVpadal, &Assembler::vpadal, cond, dt, rd, rm);  in vpadal()
22245     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vpadd()  argument
22254                    rm.Encode(5, 0));  in vpadd()
22263                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpadd()
22273                 rm.Encode(5, 0));  in vpadd()
22281                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpadd()
22286   Delegate(kVpadd, &Assembler::vpadd, cond, dt, rd, rn, rm);  in vpadd()
22292                        DRegister rm) {  in vpaddl()  argument
22302                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vpaddl()
22313                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vpaddl()
22318   Delegate(kVpaddl, &Assembler::vpaddl, cond, dt, rd, rm);  in vpaddl()
22324                        QRegister rm) {  in vpaddl()  argument
22334                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vpaddl()
22345                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vpaddl()
22350   Delegate(kVpaddl, &Assembler::vpaddl, cond, dt, rd, rm);  in vpaddl()
22354     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vpmax()  argument
22363                    rm.Encode(5, 0));  in vpmax()
22373                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpmax()
22383                 rm.Encode(5, 0));  in vpmax()
22392                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpmax()
22397   Delegate(kVpmax, &Assembler::vpmax, cond, dt, rd, rn, rm);  in vpmax()
22401     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vpmin()  argument
22410                    rm.Encode(5, 0));  in vpmin()
22420                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpmin()
22430                 rm.Encode(5, 0));  in vpmin()
22439                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpmin()
22444   Delegate(kVpmin, &Assembler::vpmin, cond, dt, rd, rn, rm);  in vpmin()
22549 void Assembler::vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vqabs()  argument
22558                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqabs()
22568                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqabs()
22573   Delegate(kVqabs, &Assembler::vqabs, cond, dt, rd, rm);  in vqabs()
22576 void Assembler::vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vqabs()  argument
22585                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqabs()
22595                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqabs()
22600   Delegate(kVqabs, &Assembler::vqabs, cond, dt, rd, rm);  in vqabs()
22604     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vqadd()  argument
22614                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqadd()
22625                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqadd()
22630   Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);  in vqadd()
22634     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vqadd()  argument
22644                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqadd()
22655                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqadd()
22660   Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);  in vqadd()
22664     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vqdmlal()  argument
22673                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmlal()
22683                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmlal()
22688   Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, rm);  in vqdmlal()
22742     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vqdmlsl()  argument
22751                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmlsl()
22761                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmlsl()
22766   Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, rm);  in vqdmlsl()
22820     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vqdmulh()  argument
22829                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmulh()
22839                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmulh()
22844   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);  in vqdmulh()
22848     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vqdmulh()  argument
22857                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmulh()
22867                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmulh()
22872   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);  in vqdmulh()
22876     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {  in vqdmulh()  argument
22883         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmulh()
22884          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmulh()
22885           (rm.GetLane() <= 1))) &&  in vqdmulh()
22889                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmulh()
22897         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmulh()
22898          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmulh()
22899           (rm.GetLane() <= 1))) &&  in vqdmulh()
22903                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmulh()
22908   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);  in vqdmulh()
22912     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {  in vqdmulh()  argument
22919         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmulh()
22920          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmulh()
22921           (rm.GetLane() <= 1))) &&  in vqdmulh()
22925                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmulh()
22933         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmulh()
22934          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmulh()
22935           (rm.GetLane() <= 1))) &&  in vqdmulh()
22939                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmulh()
22944   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);  in vqdmulh()
22948     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vqdmull()  argument
22957                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmull()
22967                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmull()
22972   Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);  in vqdmull()
22976     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {  in vqdmull()  argument
22983         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmull()
22984          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmull()
22985           (rm.GetLane() <= 1))) &&  in vqdmull()
22989                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmull()
22997         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmull()
22998          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmull()
22999           (rm.GetLane() <= 1))) &&  in vqdmull()
23003                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmull()
23008   Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);  in vqdmull()
23014                        QRegister rm) {  in vqmovn()  argument
23024                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqmovn()
23035                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqmovn()
23040   Delegate(kVqmovn, &Assembler::vqmovn, cond, dt, rd, rm);  in vqmovn()
23046                         QRegister rm) {  in vqmovun()  argument
23055                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqmovun()
23065                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqmovun()
23070   Delegate(kVqmovun, &Assembler::vqmovun, cond, dt, rd, rm);  in vqmovun()
23073 void Assembler::vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vqneg()  argument
23082                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqneg()
23092                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqneg()
23097   Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm);  in vqneg()
23100 void Assembler::vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vqneg()  argument
23109                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqneg()
23119                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqneg()
23124   Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm);  in vqneg()
23128     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vqrdmulh()  argument
23137                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqrdmulh()
23147                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqrdmulh()
23152   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);  in vqrdmulh()
23156     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vqrdmulh()  argument
23165                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqrdmulh()
23175                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqrdmulh()
23180   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);  in vqrdmulh()
23184     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {  in vqrdmulh()  argument
23191         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqrdmulh()
23192          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqrdmulh()
23193           (rm.GetLane() <= 1))) &&  in vqrdmulh()
23197                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqrdmulh()
23205         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqrdmulh()
23206          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqrdmulh()
23207           (rm.GetLane() <= 1))) &&  in vqrdmulh()
23211                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqrdmulh()
23216   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);  in vqrdmulh()
23220     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {  in vqrdmulh()  argument
23227         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqrdmulh()
23228          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqrdmulh()
23229           (rm.GetLane() <= 1))) &&  in vqrdmulh()
23233                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqrdmulh()
23241         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqrdmulh()
23242          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqrdmulh()
23243           (rm.GetLane() <= 1))) &&  in vqrdmulh()
23247                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqrdmulh()
23252   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);  in vqrdmulh()
23256     Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {  in vqrshl()  argument
23266                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqrshl()
23277                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqrshl()
23282   Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);  in vqrshl()
23286     Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {  in vqrshl()  argument
23296                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqrshl()
23307                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqrshl()
23312   Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);  in vqrshl()
23318                         QRegister rm,  in vqrshrn()  argument
23334                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vqrshrn()
23346                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqrshrn()
23358                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vqrshrn()
23368                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqrshrn()
23375   Delegate(kVqrshrn, &Assembler::vqrshrn, cond, dt, rd, rm, operand);  in vqrshrn()
23381                          QRegister rm,  in vqrshrun()  argument
23397                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqrshrun()
23406                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vqrshrun()
23418                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqrshrun()
23426                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vqrshrun()
23433   Delegate(kVqrshrun, &Assembler::vqrshrun, cond, dt, rd, rm, operand);  in vqrshrun()
23439                       DRegister rm,  in vqshl()  argument
23453                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqshl()
23464                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqshl()
23482                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshl()
23495                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshl()
23502   Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);  in vqshl()
23508                       QRegister rm,  in vqshl()  argument
23522                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqshl()
23533                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqshl()
23551                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshl()
23564                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshl()
23571   Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);  in vqshl()
23577                        DRegister rm,  in vqshlu()  argument
23593                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshlu()
23606                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshlu()
23613   Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);  in vqshlu()
23619                        QRegister rm,  in vqshlu()  argument
23635                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshlu()
23648                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshlu()
23655   Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);  in vqshlu()
23661                        QRegister rm,  in vqshrn()  argument
23677                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vqshrn()
23689                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshrn()
23701                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vqshrn()
23711                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshrn()
23718   Delegate(kVqshrn, &Assembler::vqshrn, cond, dt, rd, rm, operand);  in vqshrn()
23724                         QRegister rm,  in vqshrun()  argument
23740                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshrun()
23749                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vqshrun()
23761                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshrun()
23769                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vqshrun()
23776   Delegate(kVqshrun, &Assembler::vqshrun, cond, dt, rd, rm, operand);  in vqshrun()
23780     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vqsub()  argument
23790                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqsub()
23801                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqsub()
23806   Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);  in vqsub()
23810     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vqsub()  argument
23820                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqsub()
23831                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqsub()
23836   Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);  in vqsub()
23840     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {  in vraddhn()  argument
23849                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vraddhn()
23859                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vraddhn()
23864   Delegate(kVraddhn, &Assembler::vraddhn, cond, dt, rd, rn, rm);  in vraddhn()
23870                        DRegister rm) {  in vrecpe()  argument
23880                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrecpe()
23891                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrecpe()
23896   Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm);  in vrecpe()
23902                        QRegister rm) {  in vrecpe()  argument
23912                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrecpe()
23923                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrecpe()
23928   Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm);  in vrecpe()
23932     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vrecps()  argument
23940                    rm.Encode(5, 0));  in vrecps()
23950                 rm.Encode(5, 0));  in vrecps()
23955   Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);  in vrecps()
23959     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vrecps()  argument
23967                    rm.Encode(5, 0));  in vrecps()
23977                 rm.Encode(5, 0));  in vrecps()
23982   Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);  in vrecps()
23988                        DRegister rm) {  in vrev16()  argument
23997                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev16()
24007                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev16()
24012   Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm);  in vrev16()
24018                        QRegister rm) {  in vrev16()  argument
24027                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev16()
24037                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev16()
24042   Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm);  in vrev16()
24048                        DRegister rm) {  in vrev32()  argument
24057                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev32()
24067                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev32()
24072   Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm);  in vrev32()
24078                        QRegister rm) {  in vrev32()  argument
24087                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev32()
24097                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev32()
24102   Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm);  in vrev32()
24108                        DRegister rm) {  in vrev64()  argument
24117                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev64()
24127                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev64()
24132   Delegate(kVrev64, &Assembler::vrev64, cond, dt, rd, rm);  in vrev64()
24138                        QRegister rm) {  in vrev64()  argument
24147                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev64()
24157                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev64()
24162   Delegate(kVrev64, &Assembler::vrev64, cond, dt, rd, rm);  in vrev64()
24166     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vrhadd()  argument
24176                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrhadd()
24187                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrhadd()
24192   Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);  in vrhadd()
24196     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vrhadd()  argument
24206                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrhadd()
24217                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrhadd()
24222   Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);  in vrhadd()
24225 void Assembler::vrinta(DataType dt, DRegister rd, DRegister rm) {  in vrinta()  argument
24233                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24239       EmitT32_32(0xfeb80b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24247               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24252       EmitA32(0xfeb80b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24256   Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);  in vrinta()
24259 void Assembler::vrinta(DataType dt, QRegister rd, QRegister rm) {  in vrinta()  argument
24267                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24275               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24279   Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);  in vrinta()
24282 void Assembler::vrinta(DataType dt, SRegister rd, SRegister rm) {  in vrinta()  argument
24288       EmitT32_32(0xfeb80a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24295       EmitA32(0xfeb80a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24299   Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);  in vrinta()
24302 void Assembler::vrintm(DataType dt, DRegister rd, DRegister rm) {  in vrintm()  argument
24310                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24316       EmitT32_32(0xfebb0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24324               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24329       EmitA32(0xfebb0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24333   Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);  in vrintm()
24336 void Assembler::vrintm(DataType dt, QRegister rd, QRegister rm) {  in vrintm()  argument
24344                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24352               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24356   Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);  in vrintm()
24359 void Assembler::vrintm(DataType dt, SRegister rd, SRegister rm) {  in vrintm()  argument
24365       EmitT32_32(0xfebb0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24372       EmitA32(0xfebb0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24376   Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);  in vrintm()
24379 void Assembler::vrintn(DataType dt, DRegister rd, DRegister rm) {  in vrintn()  argument
24387                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24393       EmitT32_32(0xfeb90b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24401               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24406       EmitA32(0xfeb90b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24410   Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);  in vrintn()
24413 void Assembler::vrintn(DataType dt, QRegister rd, QRegister rm) {  in vrintn()  argument
24421                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24429               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24433   Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);  in vrintn()
24436 void Assembler::vrintn(DataType dt, SRegister rd, SRegister rm) {  in vrintn()  argument
24442       EmitT32_32(0xfeb90a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24449       EmitA32(0xfeb90a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24453   Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);  in vrintn()
24456 void Assembler::vrintp(DataType dt, DRegister rd, DRegister rm) {  in vrintp()  argument
24464                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24470       EmitT32_32(0xfeba0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24478               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24483       EmitA32(0xfeba0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24487   Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);  in vrintp()
24490 void Assembler::vrintp(DataType dt, QRegister rd, QRegister rm) {  in vrintp()  argument
24498                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24506               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24510   Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);  in vrintp()
24513 void Assembler::vrintp(DataType dt, SRegister rd, SRegister rm) {  in vrintp()  argument
24519       EmitT32_32(0xfeba0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24526       EmitA32(0xfeba0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24530   Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);  in vrintp()
24536                        SRegister rm) {  in vrintr()  argument
24542       EmitT32_32(0xeeb60a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintr()
24550               rm.Encode(5, 0));  in vrintr()
24554   Delegate(kVrintr, &Assembler::vrintr, cond, dt, rd, rm);  in vrintr()
24560                        DRegister rm) {  in vrintr()  argument
24566       EmitT32_32(0xeeb60b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintr()
24574               rm.Encode(5, 0));  in vrintr()
24578   Delegate(kVrintr, &Assembler::vrintr, cond, dt, rd, rm);  in vrintr()
24584                        DRegister rm) {  in vrintx()  argument
24592                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24598       EmitT32_32(0xeeb70b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24606               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24612               rm.Encode(5, 0));  in vrintx()
24616   Delegate(kVrintx, &Assembler::vrintx, cond, dt, rd, rm);  in vrintx()
24619 void Assembler::vrintx(DataType dt, QRegister rd, QRegister rm) {  in vrintx()  argument
24627                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24635               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24639   Delegate(kVrintx, &Assembler::vrintx, dt, rd, rm);  in vrintx()
24645                        SRegister rm) {  in vrintx()  argument
24651       EmitT32_32(0xeeb70a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24659               rm.Encode(5, 0));  in vrintx()
24663   Delegate(kVrintx, &Assembler::vrintx, cond, dt, rd, rm);  in vrintx()
24669                        DRegister rm) {  in vrintz()  argument
24677                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24683       EmitT32_32(0xeeb60bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24691               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24697               rm.Encode(5, 0));  in vrintz()
24701   Delegate(kVrintz, &Assembler::vrintz, cond, dt, rd, rm);  in vrintz()
24704 void Assembler::vrintz(DataType dt, QRegister rd, QRegister rm) {  in vrintz()  argument
24712                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24720               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24724   Delegate(kVrintz, &Assembler::vrintz, dt, rd, rm);  in vrintz()
24730                        SRegister rm) {  in vrintz()  argument
24736       EmitT32_32(0xeeb60ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24744               rm.Encode(5, 0));  in vrintz()
24748   Delegate(kVrintz, &Assembler::vrintz, cond, dt, rd, rm);  in vrintz()
24752     Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {  in vrshl()  argument
24762                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vrshl()
24773                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vrshl()
24778   Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);  in vrshl()
24782     Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {  in vrshl()  argument
24792                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vrshl()
24803                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vrshl()
24808   Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);  in vrshl()
24814                       DRegister rm,  in vrshr()  argument
24830                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshr()
24838             EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vrshr()
24839                        rm.Encode(5, 0));  in vrshr()
24852                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshr()
24859             EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vrshr()
24860                     rm.Encode(5, 0));  in vrshr()
24867   Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);  in vrshr()
24873                       QRegister rm,  in vrshr()  argument
24889                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshr()
24897             EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vrshr()
24898                        rm.Encode(5, 0));  in vrshr()
24911                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshr()
24918             EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vrshr()
24919                     rm.Encode(5, 0));  in vrshr()
24926   Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);  in vrshr()
24932                        QRegister rm,  in vrshrn()  argument
24948                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshrn()
24957                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vrshrn()
24969                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshrn()
24977                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vrshrn()
24984   Delegate(kVrshrn, &Assembler::vrshrn, cond, dt, rd, rm, operand);  in vrshrn()
24990                         DRegister rm) {  in vrsqrte()  argument
25000                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrsqrte()
25011                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrsqrte()
25016   Delegate(kVrsqrte, &Assembler::vrsqrte, cond, dt, rd, rm);  in vrsqrte()
25022                         QRegister rm) {  in vrsqrte()  argument
25032                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrsqrte()
25043                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrsqrte()
25048   Delegate(kVrsqrte, &Assembler::vrsqrte, cond, dt, rd, rm);  in vrsqrte()
25052     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vrsqrts()  argument
25060                    rm.Encode(5, 0));  in vrsqrts()
25070                 rm.Encode(5, 0));  in vrsqrts()
25075   Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);  in vrsqrts()
25079     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vrsqrts()  argument
25087                    rm.Encode(5, 0));  in vrsqrts()
25097                 rm.Encode(5, 0));  in vrsqrts()
25102   Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);  in vrsqrts()
25108                       DRegister rm,  in vrsra()  argument
25124                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrsra()
25137                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrsra()
25144   Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);  in vrsra()
25150                       QRegister rm,  in vrsra()  argument
25166                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrsra()
25179                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrsra()
25186   Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);  in vrsra()
25190     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {  in vrsubhn()  argument
25199                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrsubhn()
25209                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrsubhn()
25214   Delegate(kVrsubhn, &Assembler::vrsubhn, cond, dt, rd, rn, rm);  in vrsubhn()
25217 void Assembler::vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vseleq()  argument
25224                  rm.Encode(5, 0));  in vseleq()
25232               rm.Encode(5, 0));  in vseleq()
25236   Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);  in vseleq()
25239 void Assembler::vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vseleq()  argument
25246                  rm.Encode(5, 0));  in vseleq()
25254               rm.Encode(5, 0));  in vseleq()
25258   Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);  in vseleq()
25261 void Assembler::vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vselge()  argument
25268                  rm.Encode(5, 0));  in vselge()
25276               rm.Encode(5, 0));  in vselge()
25280   Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);  in vselge()
25283 void Assembler::vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vselge()  argument
25290                  rm.Encode(5, 0));  in vselge()
25298               rm.Encode(5, 0));  in vselge()
25302   Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);  in vselge()
25305 void Assembler::vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vselgt()  argument
25312                  rm.Encode(5, 0));  in vselgt()
25320               rm.Encode(5, 0));  in vselgt()
25324   Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);  in vselgt()
25327 void Assembler::vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vselgt()  argument
25334                  rm.Encode(5, 0));  in vselgt()
25342               rm.Encode(5, 0));  in vselgt()
25346   Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);  in vselgt()
25349 void Assembler::vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vselvs()  argument
25356                  rm.Encode(5, 0));  in vselvs()
25364               rm.Encode(5, 0));  in vselvs()
25368   Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);  in vselvs()
25371 void Assembler::vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vselvs()  argument
25378                  rm.Encode(5, 0));  in vselvs()
25386               rm.Encode(5, 0));  in vselvs()
25390   Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);  in vselvs()
25396                      DRegister rm,  in vshl()  argument
25412                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshl()
25425                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshl()
25442                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vshl()
25453                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vshl()
25459   Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);  in vshl()
25465                      QRegister rm,  in vshl()  argument
25481                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshl()
25494                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshl()
25511                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vshl()
25522                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vshl()
25528   Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);  in vshl()
25534                       DRegister rm,  in vshll()  argument
25550                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshll()
25559                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vshll()
25571                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshll()
25579                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vshll()
25586   Delegate(kVshll, &Assembler::vshll, cond, dt, rd, rm, operand);  in vshll()
25592                      DRegister rm,  in vshr()  argument
25608                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshr()
25616             EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vshr()
25617                        rm.Encode(5, 0));  in vshr()
25630                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshr()
25637             EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vshr()
25638                     rm.Encode(5, 0));  in vshr()
25645   Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);  in vshr()
25651                      QRegister rm,  in vshr()  argument
25667                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshr()
25675             EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vshr()
25676                        rm.Encode(5, 0));  in vshr()
25689                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshr()
25696             EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vshr()
25697                     rm.Encode(5, 0));  in vshr()
25704   Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);  in vshr()
25710                       QRegister rm,  in vshrn()  argument
25726                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshrn()
25735                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vshrn()
25747                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshrn()
25755                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vshrn()
25762   Delegate(kVshrn, &Assembler::vshrn, cond, dt, rd, rm, operand);  in vshrn()
25768                      DRegister rm,  in vsli()  argument
25784                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsli()
25797                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsli()
25804   Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);  in vsli()
25810                      QRegister rm,  in vsli()  argument
25826                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsli()
25839                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsli()
25846   Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);  in vsli()
25849 void Assembler::vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) {  in vsqrt()  argument
25855       EmitT32_32(0xeeb10ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vsqrt()
25863               rm.Encode(5, 0));  in vsqrt()
25867   Delegate(kVsqrt, &Assembler::vsqrt, cond, dt, rd, rm);  in vsqrt()
25870 void Assembler::vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vsqrt()  argument
25876       EmitT32_32(0xeeb10bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vsqrt()
25884               rm.Encode(5, 0));  in vsqrt()
25888   Delegate(kVsqrt, &Assembler::vsqrt, cond, dt, rd, rm);  in vsqrt()
25894                      DRegister rm,  in vsra()  argument
25910                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsra()
25923                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsra()
25930   Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);  in vsra()
25936                      QRegister rm,  in vsra()  argument
25952                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsra()
25965                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsra()
25972   Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);  in vsra()
25978                      DRegister rm,  in vsri()  argument
25994                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsri()
26007                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsri()
26014   Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);  in vsri()
26020                      QRegister rm,  in vsri()  argument
26036                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsri()
26049                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsri()
26056   Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);  in vsri()
26255     Register rm = operand.GetOffsetRegister();  in vst1()  local
26261       // VST1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vst1()
26264           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst1()
26287                      (rn.GetCode() << 16) | rm.GetCode());  in vst1()
26292       // VST1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vst1()
26294           (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&  in vst1()
26301                      rm.GetCode());  in vst1()
26307       // VST1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vst1()
26310           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst1()
26333                   (rn.GetCode() << 16) | rm.GetCode());  in vst1()
26337       // VST1{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vst1()
26339           (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&  in vst1()
26345                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vst1()
26537     Register rm = operand.GetOffsetRegister();  in vst2()  local
26542       // VST2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vst2()
26547           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst2()
26563                      (rn.GetCode() << 16) | rm.GetCode());  in vst2()
26568       // VST2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vst2()
26572           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst2()
26578                      rm.GetCode());  in vst2()
26584       // VST2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vst2()
26589           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst2()
26605                   (rn.GetCode() << 16) | rm.GetCode());  in vst2()
26609       // VST2{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vst2()
26613           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst2()
26618                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vst2()
26711     Register rm = operand.GetOffsetRegister();  in vst3()  local
26715       // VST3{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vst3()
26719           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst3()
26726                      (rn.GetCode() << 16) | rm.GetCode());  in vst3()
26732       // VST3{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vst3()
26736           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst3()
26743                   (rn.GetCode() << 16) | rm.GetCode());  in vst3()
26823     Register rm = operand.GetOffsetRegister();  in vst3()  local
26827       // VST3{<c>}{<q>}.<dt> <list>, [<Rn>], #<Rm> ; T1  in vst3()
26838                      rm.GetCode());  in vst3()
26844       // VST3{<c>}{<q>}.<dt> <list>, [<Rn>], #<Rm> ; A1  in vst3()
26854                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vst3()
27006     Register rm = operand.GetOffsetRegister();  in vst4()  local
27011       // VST4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vst4()
27015           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst4()
27022                      (rn.GetCode() << 16) | rm.GetCode());  in vst4()
27027       // VST4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; T1  in vst4()
27031           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst4()
27037                      rm.GetCode());  in vst4()
27043       // VST4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vst4()
27047           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst4()
27054                   (rn.GetCode() << 16) | rm.GetCode());  in vst4()
27058       // VST4{<c>}{<q>}.<dt> <list>, [<Rn>{:<align>}], <Rm> ; A1  in vst4()
27062           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst4()
27067                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vst4()
27356     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vsub()  argument
27365                    rm.Encode(5, 0));  in vsub()
27373                  rm.Encode(5, 0));  in vsub()
27381                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27391                 rm.Encode(5, 0));  in vsub()
27398               rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27405                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27410   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);  in vsub()
27414     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vsub()  argument
27423                    rm.Encode(5, 0));  in vsub()
27432                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27442                 rm.Encode(5, 0));  in vsub()
27450                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27455   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);  in vsub()
27459     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vsub()  argument
27466                  rm.Encode(5, 0));  in vsub()
27474               rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27478   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);  in vsub()
27482     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {  in vsubhn()  argument
27491                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubhn()
27501                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubhn()
27506   Delegate(kVsubhn, &Assembler::vsubhn, cond, dt, rd, rn, rm);  in vsubhn()
27510     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vsubl()  argument
27520                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubl()
27531                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubl()
27536   Delegate(kVsubl, &Assembler::vsubl, cond, dt, rd, rn, rm);  in vsubl()
27540     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {  in vsubw()  argument
27550                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubw()
27561                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubw()
27566   Delegate(kVsubw, &Assembler::vsubw, cond, dt, rd, rn, rm);  in vsubw()
27569 void Assembler::vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vswp()  argument
27576       EmitT32_32(0xffb20000U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vswp()
27583       EmitA32(0xf3b20000U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vswp()
27587   Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm);  in vswp()
27590 void Assembler::vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vswp()  argument
27597       EmitT32_32(0xffb20040U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vswp()
27604       EmitA32(0xf3b20040U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vswp()
27608   Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm);  in vswp()
27615                      DRegister rm) {  in vtbl()  argument
27626                    (len_encoding << 8) | rm.Encode(5, 0));  in vtbl()
27639                 (len_encoding << 8) | rm.Encode(5, 0));  in vtbl()
27644   Delegate(kVtbl, &Assembler::vtbl, cond, dt, rd, nreglist, rm);  in vtbl()
27651                      DRegister rm) {  in vtbx()  argument
27662                    (len_encoding << 8) | rm.Encode(5, 0));  in vtbx()
27675                 (len_encoding << 8) | rm.Encode(5, 0));  in vtbx()
27680   Delegate(kVtbx, &Assembler::vtbx, cond, dt, rd, nreglist, rm);  in vtbx()
27683 void Assembler::vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vtrn()  argument
27692                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vtrn()
27702                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vtrn()
27707   Delegate(kVtrn, &Assembler::vtrn, cond, dt, rd, rm);  in vtrn()
27710 void Assembler::vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vtrn()  argument
27719                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vtrn()
27729                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vtrn()
27734   Delegate(kVtrn, &Assembler::vtrn, cond, dt, rd, rm);  in vtrn()
27738     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vtst()  argument
27747                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vtst()
27757                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vtst()
27762   Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);  in vtst()
27766     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vtst()  argument
27775                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vtst()
27785                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vtst()
27790   Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);  in vtst()
27793 void Assembler::vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vuzp()  argument
27802                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27810         EmitT32_32(0xffba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27820                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27827         EmitA32(0xf3ba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27832   Delegate(kVuzp, &Assembler::vuzp, cond, dt, rd, rm);  in vuzp()
27835 void Assembler::vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vuzp()  argument
27844                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27854                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27859   Delegate(kVuzp, &Assembler::vuzp, cond, dt, rd, rm);  in vuzp()
27862 void Assembler::vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vzip()  argument
27871                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27879         EmitT32_32(0xffba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27889                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27896         EmitA32(0xf3ba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27901   Delegate(kVzip, &Assembler::vzip, cond, dt, rd, rm);  in vzip()
27904 void Assembler::vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vzip()  argument
27913                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27923                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27928   Delegate(kVzip, &Assembler::vzip, cond, dt, rd, rm);  in vzip()